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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. DRV10987 slvse89a ? august 2017 ? revised november 2017 DRV10987 12- to 24-v, three-phase, sensorless bldc motor driver 1 1 features 1 ? operation voltage range: ? motor operation, 6.2 v to 28 v ? total driver h + l r ds(on) ? 250 m at t a = 25 c ? drive current: 2-a continuous winding current (3-a peak) ? sensorless sinusoidal 180 commutation scheme ? configurable output pwm slew rate and frequency for emi management ? initial position-detect algorithm to avoid back- spin during start-up ? no external sense resistor required ? flexible user interface options: ? i 2 c interface: access registers for command and feedback ? dedicated speed pin: accepts either analog or pwm input ? dedicated fg pin: provides tach feedback ? spin-up profile can be customized with eeprom ? forward-reverse control with dir pin ? integrated buck converter, 5 ? v, 100-ma ? integrated ldo, 3.3 ? v, 20-ma ? standby current, 8.5-ma ? supply current of 8.5 ma with standby version (DRV10987s) ? supply current of 48 a with sleep version (DRV10987d) ? protection features ? overcurrent protection (phase-to-phase, phase-to-gnd and phase-to-v cc short circuits) ? lock detection to detect rotor lock condition ? anti-voltage surge (avs) protection ? undervoltae lockout (uvlo) ? overvoltage protection ? thermal warning and shutdown ? thermally enhanced package 2 applications ? pedestal and ceiling fans ? air purifiers and humidifiers ? dryer circulation fans ? drain and water pumps ? three-phase bldc and pmsm motors 3 description the DRV10987 device is a 3-phase sensorless 180 sinusodial motor driver with integrated power mosfets, which can provide continuous drive current up to 2 a. the device is specifically designed for cost-sensitive, low-noise, low-external-component- count fan and pump applications. ? the DRV10987 device delivers current to the motor with supply voltage as low as 6.2 v. if the power supply voltage is higher than 28 v, the device stops driving the motor and protects the DRV10987 circuitry. device information (1) part number package body size (nom) DRV10987 htssop (24) 7.80 mm 6.40 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. device comparison part number version DRV10987d sleep version DRV10987s standby version application schematic productfolder 1 2 3 4 5 6 7 89 10 11 12 24 23 22 21 20 1918 17 16 15 14 13 vcp cpp cpn sw swgnd vreg v1p8 gnd v3p3 scl sda fg vcc vcc ww vv uu pgnd pgnd dir speed interface to microcontroller 0.1 f 10 nf 47 h 10 f 1 f 10 f 1 f vcc 5 v m copyright ? 2017, texas instruments incorporated 4.75 k w 4.75 k w support &community tools & software technical documents ordernow
2 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 description (continued) ........................................ 3 6 pin configuration and functions ......................... 3 7 specifications ......................................................... 5 7.1 absolute maximum ratings ...................................... 5 7.2 esd ratings .............................................................. 5 7.3 recommended operating conditions ....................... 6 7.4 thermal information .................................................. 6 7.5 electrical characteristics ........................................... 7 7.6 typical characteristics ............................................ 14 8 detailed description ............................................ 15 8.1 overview ................................................................. 15 8.2 functional block diagram ....................................... 16 8.3 feature description ................................................. 16 8.4 device functional modes ........................................ 23 8.5 register maps ......................................................... 49 9 application and implementation ........................ 66 9.1 application information ............................................ 66 9.2 typical application ................................................. 66 10 power supply recommendations ..................... 69 11 layout ................................................................... 69 11.1 layout guidelines ................................................. 69 11.2 layout example .................................................... 69 12 device and documentation support ................. 70 12.1 trademarks ........................................................... 70 12.2 electrostatic discharge caution ............................ 70 12.3 receiving notification of documentation updates 70 12.4 community resources .......................................... 70 12.5 glossary ................................................................ 70 13 mechanical, packaging, and orderable information ........................................................... 70 4 revision history changes from original (august 2017) to revision a page ? added supply current for standby and sleep versions to the features list ............................................................................ 1 ? added device comparison table ........................................................................................................................................... 1 ? added a discussion of the sleep and standby versions of the device to the description (continued) section ...................... 3 ? added table note to table 1 , conditions to enter or exit sleep or standby condition ........................................................ 20 ? added subsection, required sequence to enter sleep mode ............................................................................................. 21
3 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 5 description (continued) the DRV10987 device uses a proprietary sensorless control scheme to provide continuous sinusoidal drive, which significantly reduces the pure tone acoustics that typically occur as a result of commutation. the interface to the device is designed to be simple and flexible. the motor can be controlled directly through pwm, analog, or i 2 c inputs. motor speed feedback is available through both the fg pin and the i 2 c interface simultaneously. the DRV10987 device features an integrated buck regulator to step down the supply voltage efficiently to 5 v for powering both internal and external circuits. the 3.3-v ldo also may be used to provide power for external circuits. the standby-mode (8.5 ma) version (DRV10987s) leaves the regulator running, and the sleep-mode (48 a) version (DRV10987d) shuts the regulator off. throughout this data sheet, the DRV10987 part number is used for both devices, that is, DRV10987d (sleep version) and DRV10987s (standby version), except for specific discussions of sleep vs standby functionality. an i 2 c interface allows the user to reprogram specific motor parameters in registers and to program the eeprom to help optimize the performance for a given application. the DRV10987 device is available in a thermally-efficient htssop, 24-pin package with an exposed thermal pad. the operating ambient temperature is specified from ? 40 c to 125 c. 6 pin configuration and functions pwp powerpad ? package 24-pin htssop with exposed thermal pad top view not to scale thermal pad 1 vcp 24 vcc 2 cpp 23 vcc 3 cpn 22 w 4 sw 21 w 5 swgnd 20 v 6 vreg 19 v 7 v1p8 18 u 8 gnd 17 u 9 v3p3 16 pgnd 10 scl 15 pgnd 11 sda 14 dir 12 fg 13 speed
4 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) i = input, o = output, i/o = input/output, p = power pin functions pin type (1) description n/ame htssop cpn 3 p charge pump pin 1, use a ceramic capacitor between cpn and cpp cpp 2 p charge pump pin 2, use a ceramic capacitor between cpn and cpp dir 14 i direction; when low, phase driving sequence is u v w when high, phase driving sequence is u w v fg 12 o fg signal output indicates speed of motor gnd 8 p digital and analog ground pgnd 15, 16 p power ground scl 10 i i 2 c clock signal sda 11 i/o i 2 c data signal speed 13 i speed control signal for pwm or analog input speed command sw 4 o step-down regulator switching node output swgnd 5 p step-down regulator ground u 17, 18 o motor u phase v 19, 20 o motor v phase v1p8 7 p internal 1.8-v digital core voltage. v1p8 capacitor must connect to gnd. this is an output, but is not specified to drive external loads. v3p3 9 p internal 3.3-v supply voltage. v3p3 capacitor must connect to gnd. this is an output and may drive external loads not to exceed i v3p3_max . v cc 23, 24 p device power supply vcp 1 p charge pump output, use a ceramic capacitor between vcp and v cc vreg 6 p step-down regulator output and feedback point w 21, 22 o motor w phase thermal pad (gnd) ? p the exposed thermal pad must be electrically connected to the ground plane by soldering to the pcb for proper operation, and connected to the bottom side of the pcb through vias for better thermal spreading.
5 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to the ground terminal (gnd) unless otherwise noted. 7 specifications 7.1 absolute maximum ratings over operating ambient temperature range (1) min max unit input voltage (2) v cc ? 0.3 28 v v cc during overvolatge protection(v cc slew rate < 10 v/ms) ? 0.3 45 speed ? 0.3 4 pgnd, swgnd ? 0.3 0.3 scl, sda ? 0.3 4 dir ? 0.3 4 output voltage (2) u, v, w ? 1 30 v sw ? 1 30 vreg ? 0.3 7 fg ? 0.3 4 vcp ? 0.3 v cc + 6 cpn ? 0.3 30 cpp ? 0.3 v cc + 6 v3p3 ? 0.3 4 v1p8 ? 0.3 2.5 t j_max maximum junction temperature ? 40 150 c t stg storage temperature ? 55 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 2000 v charged device model (cdm), per jedec specification jesd22-c101, all pins (2) 750
6 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3 recommended operating conditions min nom max unit supply voltage v cc , register contents preserved 4.5 12 45 v v cc , motor operational 6.2 12 28 voltage range u, v, w ? 0.7 29 v scl, sda, fg, speed, dir , nfault ? 0.1 3.3 3.6 pgnd, gnd, swgnd ? 0.1 0.1 vcp, cpp ? 0.1 v cc + 5 cpn ? 0.1 v cc sw ? 0.7 v cc current range step-down regulator with inductor (buck mode) output current 100 ma step-down regulator with resistor (linear mode) output current 5 v3p3 ldo output current (no load on vreg and step-down regulator in linear mode) 5 t a operating ambient temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 7.4 thermal information thermal metric (1) DRV10987 unit pwp (htssop) 24 pins r ja junction-to-ambient thermal resistance 36.1 c/w r jc(top) junction-to-case (top) thermal resistance 17.4 c/w r jb junction-to-board thermal resistance 14.8 c/w jt junction-to-top characterization parameter 0.4 c/w jb junction-to-board characterization parameter 14.5 c/w r jc(bot) junction-to-case (bottom) thermal resistance 1.1 c/w
7 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.5 electrical characteristics over operating voltage and ambient temperature range (unless otherwise noted) parameter test conditions min typ max unit supply current (DRV10987d) i ccsleep1 sleep current v speed = 0 v; v cc = 12 v; t a = 25 48 54 a v speed = 0 v; v cc = 12 v; across temperature 81 i cc active current v speed > 0 v; step-down regulator with inductor (buck mode); no motor load 10 15 ma v speed > 0 v; step-down regulator with resistor (linear mode); no motor load 13 16 i ccsleep2 sleep current with turtle mode disabled v speed = 0 v; v cc = 12 v; t a = 25 ; turtle mode disabled 48 54 a i ccsleep1 sleep current v speed = 0 v; v cc = 12 v; across temp; turtle mode disabled 50 a supply current (DRV10987s) i ccstby standby current v speed = 0 v; step-down regulator with inductor (buck mode) 8.5 14 ma v speed = 0 v; buck regulator with resistor (linear mode) 11 15 i cc active current v speed > 0 v; buck regulator with inductor; no motor load 10 15 ma v speed > 0 v; buck regulator with resistor; no motor load 13 16 uvlo v uvlo_r uvlo rising threshold voltage 5.8 6 6.2 v v uvlo_f uvlo falling threshold voltage 5.6 5.8 6 v v uvlo_hys uvlo threshold voltage hysteresis 170 195 220 mv v vcp_uvlo_r charge pump uvlo rising threshold (v (vcp) - v cc ) 3.6 3.8 4.2 v v vcp_uvlo_f charge pump uvlo falling threshold (v (vcp) - v cc ) 3.5 3.65 3.75 v v v1p8_uvlo_r v1p8 uvlo rising threshold 1.5 1.6 1.7 v v v1p8_uvlo_f v1p8 uvlo falling threshold 1.4 1.55 1.65 v v v3p3_uvlo_r v3p3 uvlo rising threshold 2.7 2.85 2.95 v v v3p3_uvlo_f v3p3 uvlo falling threshold 2.5 2.7 2.8 v v vreg_uvlo_r vreg uvlo rising threshold 4 4.2 4.3 v v vreg_uvlo_f vreg uvlo falling threshold 3.9 4.2 v ldo output v3p3 output voltage step-down regulator with inductor (buck mode), 20-ma load 3.1 3.3 3.5 v step-down regulator with resistor (linear mode), no load 3.1 3.3 3.5 i v3p3_max maximum load from v3p3 step-down regulator with inductor (buck mode) 20 ma v1p8 output voltage no load 1.7 1.8 1.9 v
8 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over operating voltage and ambient temperature range (unless otherwise noted) parameter test conditions min typ max unit step-down regulator v reg regulator output voltage l sw = 47 h, c sw = 10 f i load = 100 ma 4.5 5 5.5 v r sw = 39 , c sw = 10 f i load = 5 ma 4.5 5 5.5 i reg_max_l maximum load from v reg in buck mode l sw = 47 h, c sw = 10 f 100 ma i reg_max_r maximum load from v reg in linear mode r sw = 39 , c sw = 10 f 5 ma integrated mosfet r ds(on) series resistance (h + l) t a = 25 ? c; v cc > 6.5 v; i o = 1 a 250 400 m t a = 125 ? c; v cc > 6.5v; i o = 1 a 325 550 speed ? analog mode v an/a_fs analog full-speed voltage v (v3p3) 0.9 v (v3p3) v v an/a_zs analog zero-speed voltage 0 100 mv t sam sampling period for analog voltage on speed pin 320 s v an/a_res analog voltage resolution 6.5 mv speed ? pwm digital mode v dig_ih pwm input high voltage 2.2 v v dig_il pwm input low voltage 0.6 v ? pwm pwm input frequency 0.1 100 khz
9 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over operating voltage and ambient temperature range (unless otherwise noted) parameter test conditions min typ max unit sleep mode (DRV10987d) v en_sl analog voltage to enter sleep mode spdctrlmd = 0 (analog mode) 100 mv v ex_sl analog voltage to exit sleep mode spdctrlmd = 0 (analog mode) 2.2 v t ex_sl_ana time needed to exit from sleep mode spdctrlmd = 0 (analog mode) v speed > v ex_sl 2 s t ex_sl_dr_ana time taken to drive motor after exiting from sleep mode spdctrlmd = 0 (analog mode) v speed > v en_sl ; isden = 0; brkdonethr[2:0] = 0 350 ms t ex_sl_pwm time needed to exit from sleep mode spdctrlmd = 1 (pwm mode) v speed > v dig_ih 2 s t ex_sl_dr_pwm time taken to drive motor after exiting from sleep mode spdctrlmd = 1 (pwm mode) v speed > v dig_ih ; isden = 0; brkdonethr[2:0] = 0 350 ms t en_sl_ana time needed to enter sleep mode spdctrlmd = 0 (analog mode) v speed < v en_sl ; avsinden = 0 6 ms t en_sl_pwm time needed to enter sleep mode spdctrlmd = 1 (pmw mode) v speed < v dig_il ; avsinden = 0 60 ms r pd_speed_sl internal speed pin pull down resistance to ground v speed = 0 (sleep mode) 55 k standby mode (DRV10987s) v en_sb analog voltage to enter standby mode spdctrlmd = 0 (analog mode) 100 mv v ex_sb analog voltage to exit standby mode spdctrlmd = 0 (analog mode) 0.17 v t ex_sb_ana time needed to exit from standby mode spdctrlmd = 0 (analog mode) v speed > v ex_sb 1 700 ms t ex_sb_dr_ana time taken to drive motor after exiting standby mode spdctrlmd = 0 (analog mode) v speed > v en_sb ; isden = 0; brkdonethr[2:0] = 0 350 ms t ex_sb_pwm time needed to exit from standby mode spdctrlmd = 1 (pwm mode) v speed > v dig_ih 2 s t ex_sb_dr_pwm time taken to drive motor after exiting standby mode spdctrlmd = 1 (pwm mode) v speed_duty > 0; isden = 0; brkdonethr[2:0] = 0 350 ms t en_sb_ana time needed to enter standby mode spdctrlmd = 0 (analog mode) v speed < v en_sb ; avsinden = 0 6 ms t en_sb_pwm time needed to enter standby mode spdctrlmd = 1 (pmw mode) v speed < v dig_il; avsinden = 0 60 ms digital i/o (dir input, fg output and nfault outpu t) v dir_h input high 2.2 v v dir_l input low 0.6 v v fg_oh output high voltage i o = 5 ma 3.3 v v fg_ol output low voltage i o = 5 ma 0.6 v i fg_sink output sink current vout = 0.3 v 5 ma i nfault_sink output sink current vout = 0.3 v 5 ma i 2 c serial interface v i2c_h input high 2.2 v v i2c_l input low 0.6 v f i2c i 2 c clock frequency 0 400 khz lock detection release time
10 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over operating voltage and ambient temperature range (unless otherwise noted) parameter test conditions min typ max unit t lock_off lock release time 5 s t lck_etr lock enter time 0.3 s overcurrent protection i oc_limit_hs hs overcurrent protection v cc < 28.5 v 3.5 4.25 5.5 a i oc_limit_ls ls overcurrent protection v cc < 28.5 v 3.5 4.25 5.5 a thermal shutdown t sdn junction temperature shutdown threshold 150 165 180 c t sdn_hys junction temperature shutdown hysteresis 15 20 25 c t warn junction temperature warning threshold 115 125 140 c t warn_hys temperature warning hysteresis 19 c phase driver sl ph_lh0 phase slew rate switching low to high phslew = 0; measure 20% to 80%; v cc = 12 v 85 120 145 v/ s sl ph_lh1 phase slew rate switching low to high phslew = 1; measure 20% to 80%; v cc = 12 v 60 80 100 v/ s sl ph_lh2 phase slew rate switching low to high phslew = 2; measure 20% to 80%; v cc = 12 v 38 50 62 v/ s sl ph_lh3 phase slew rate switching low to high phslew = 3; measure 20% to 80%; v cc = 12 v 27 35 44 v/ s sl ph_hl0 phase slew rate switching high to low phslew = 0; measure 80% to 20%; v cc = 12 v 85 120 145 v/ s sl ph_hl1 phase slew rate switching high to low phslew = 1; measure 80% to 20%; v cc = 12 v 59 80 100 v/ s sl ph_hl2 phase slew rate switching high to low phslew = 2; measure 80% to 20%; v cc = 12 v 36 50 60 v/ s sl ph_hl3 phase slew rate switching high to low phslew = 3; measure 80% to 20%; v cc = 12 v 25 35 45 v/ s eeprom ee prog programing voltage 6.2 v ee ret retention 10 years ee end endurance 1000 cycles overvoltage protection v ov_r overvoltage protection rising v cc threshold 28.5 29.2 30 v v ov_f overvoltage protection exit on falling v cc threshold 27.7 28.2 28.8 v v ov_hys overvoltage protection hysteresis 0.73 1 1.1 v v clamp_hi v cc to phase clamp 29.1 29.9 30.5 v v clamp_lo phase to gnd clamp 29.1 29.9 30.5 v v trl_bemf maximum bemf for turtle mode operation phase to ct 6 6.5 v current sense i sen_off_hi_in current sense offset high side current in phase current = 0 a -25 25 mv
11 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over operating voltage and ambient temperature range (unless otherwise noted) parameter test conditions min typ max unit i sen_off_hi_ou t current sense offset high side current out phase current = 0 a -25 25 mv i sen_off_lo_in current sense offset low side current in phase current = 0 a -25 25 mv i sen_off_lo_ou t current sense offset low side current out phase current = 0 a -25 25 mv i sen_gain_hi_in current sense gain high side current in 550 mv/a i sen_ gain _hi_out current sense gain high side current out 550 mv/a i sen_ gain _lo_in current sense gain low side current in 550 mv/a i sen_ gain _lo_out current sense gain low side current out 550 mv/a inductive sense i indsns inductive sense current threshold for all phases (u, v & w) targets but need to see what simulation indicates is possible inductive sense current setting 0.2a, ipdcurrthr = 0000 0.1 0.2 0.35 a inductive sense current setting 0.4a, ipdcurrthr = 0001 0.29 0.4 0.6 inductive sense current setting 0.6a, ipdcurrthr = 0010 0.47 0.6 0.82 inductive sense current setting 0.8a, ipdcurrthr = 0011 0.65 0.8 1.05 inductive sense current setting 1a, ipdcurrthr = 0100 0.83 1.0 1.28 inductive sense current setting 1.2a, ipdcurrthr = 0101 1.02 1.2 1.5 inductive sense current setting 1.4a, ipdcurrthr = 0110 1.19 1.4 1.74 inductive sense current setting 1.6a, ipdcurrthr = 0111 1.37 1.6 1.97 inductive sense current setting 1.8a, ipdcurrthr = 1000 1.55 1.8 2.21 inductive sense current setting 2a, ipdcurrthr = 1001 1.72 2.0 2.44 inductive sense current setting 2.2a, ipdcurrthr = 1010 1.9 2.2 2.68 inductive sense current setting 2.4a, ipdcurrthr = 1011 2.07 2.4 2.92 inductive sense current setting 2.6a, ipdcurrthr = 1100 2.26 2.6 3.13 inductive sense current setting 2.8a, ipdcurrthr = 1101 2.44 2.8 3.37 inductive sense current setting 3a, ipdcurrthr = 1110 2.61 3.0 3.61 t inds_res inductive sense timing resolution ipdclk < 1:0 > = 2 0.64 s i indsns_match current sense matching between phases u, v and w inductive sense current setting 1a, ipdcurrthr = 0100 -3 3 % bemf comparator
12 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over operating voltage and ambient temperature range (unless otherwise noted) parameter test conditions min typ max unit v bemf_off_uv u,v bemf comparator offset offset when comparing phase voltage at 15v -60 60 mv offset when comparing phase voltage at 0v -40 40 v bemf_off_uw u,w bemf comparator offset offset when comparing phase voltage at 15v -60 60 offset when comparing phase voltage at 0 v -40 40 bemf hys bemf comparator hysteresis bemf_hys = 0 7 20 30 mv bemf_hys = 1 17 40 51 adc v adc_ref adc reference voltage 3.3 v inl adc inl (gain-error/offset normalized) -3 3 lsb dnl adc dnl (gain-error/offset normalized) -0.9 3 lsb gain adc adc gain error -10 10 lsb offset adc adc offset error t a = 25 ? c -5 5 lsb offset adc125 adc offset error t a = 125 ? c -10 10 lsb fs pos adc full scale positive current measurement 2.45 3 a fs neg adc full scale negative current measurement -3 -2.5 a band gap v bg bandgap voltage post-trim 1.21 1.23 1.25 v oscillator f osc pre-trim frequency accuracy (ssm off) 23 25 27 mhz f osc_trimmed post-trim frequency accuracy (ssm off) ta = 25 c 24.5 25 25.5 mhz f osc_trimmed post-trim frequency accuracy (ssm off) ta = 125 c 25 27 mhz f osc_ssm frequency spread with ssm 20 25 30 mhz f ssm_step frequency step size with ssm ssmconfig[1:0] = 2b'00 (disabled) 0 % ssmconfig[1:0] = 2b'01 -5 5 ssmconfig[1:0] = 2b'10 -10 10 ssmconfig[1:0] = 2b'11 -15 15
13 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 1. DRV10987d analog mode timing figure 2. DRV10987d pwm mode timing figure 3. DRV10987s analog mode timing t ex_sb_ana speed pin internal signal (digital reset) phase pin t en_sb_ana t ex_sb_dr_ana motor drive state v en_sb v ex_sb t ex_sl_ana speed pin v1p8 phase pin t en_sl_ana t ex_sl_dr_ana motor drive state v en_sl v ex_sl t ex_sl_pwm t en_sl_pwm speed pin v1p8 phase pin motor drive state t ex_sl_dr_pwm v dig_ih v dig_il
14 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 4. DRV10987s pwm mode timing 7.6 typical characteristics figure 5. supply current vs power supply voltage figure 6. step-down regulator output vs power supply voltage t ex_sb_pwm t en_sb_pwm speed pin internal signal (digital reset) phase pin motor drive state t ex_sb_dr_pwm v dig_ih v dig_il power supply (v) supply current, standby mode (ma) 0 5 10 15 20 25 30 0 3 6 9 12 15 d001 i vcc power supply (v) switching regulator output (v) 0 5 10 15 20 25 30 4.8 4.9 5 5.1 5.2 d002
15 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8 detailed description 8.1 overview the DRV10987 device is a three-phase sensorless motor driver with integrated power mosfets that provides drive-current capability up to 2 a continuously. the device is specifically designed for low-noise, low-external- component-count motor-drive applications. the device is configurable through a simple i 2 c interface to accommodate different motor parameters and spin-up profiles for different customer applications. a 180 sensorless control scheme provides continuous sinusoidal output voltages to the motor phases to enable ultra-quiet motor operation by keeping the electrically induced torque ripple small. the DRV10987 device features extensive protection and fault-detection mechanisms to ensure reliable operation. voltage surge protection prevents the input v cc capacitor from overcharging, which typically occurs during motor deceleration. the device provides overcurrent protection without the need for an external current- sense resistor. rotor-lock detection is available through several methods. these methods can be configured with register settings to ensure reliable operation. the device provides additional protection for undervoltage lockout (uvlo) and for thermal shutdown. the commutation control algorithm continuously measures the motor phase current and periodically measures the v cc supply voltage. the device uses this information for bemf estimation, and the information is also provided through the i 2 c register interface for debug and diagnostic use in the system, if desired. a step-down regulator in buck mode efficiently steps down the supply voltage. the output of this regulator provides power for the internal circuits and can also be used to provide power for an external circuit such as a microcontroller. if providing power for an external circuit is not necessary (and to reduce system cost), configure the step-down regulator as a linear regulator by replacing the inductor with a resistor. the DRV10987 device has a flexible interface, capable of supporting both analog and digital inputs. in addition to the i 2 c interface, the device has fg, dir, and speed pins. speed is the speed ? command input pin. dir is the direction ? control input pin. fg is the speed indicator output, which shows the frequency of the motor commutation. eeprom is integrated in the DRV10987 device as memory for the motor parameter and operation settings. eeprom data transfers to the registers after power-on. the DRV10987 device can also operate in register mode. if the system includes a microcontroller communicating through the i 2 c interface, the device can dynamically update the motor parameters and operation settings by writing to the registers. in this configuration, the eeprom data is bypassed by the register settings.
16 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2 functional block diagram 8.3 feature description 8.3.1 regulators 8.3.1.1 step-down regulator the DRV10987 device includes a step-down hysteretic voltage regulator that can operate with either an external inductor or with an external resistor. the best efficiency is achieved when an external inductor (see figure 7 ) is used. the regulator output voltage is 5 v. when the regulated voltage drops by the hysteresis level, the high-side fet turns on to raise the regulated voltage back to the target of 5 v. the switching frequency of the hysteretic regulator is not constant and changes with load. if the step-down regulator is configured with an external inductor (buck mode), it can deliver current to the load as specified by i reg_max_l . if the step-down regulator is configured with an external resistor (linear mode), it can deliver current to the load as specified by i reg_max_r . active current i cc is higher in buck mode compared to linear mode. v / i sensor vcc pgnd logic core uvlo overcurrent lock thermal w v u vcpvcp vcp v cc v cc v cc pwm and analog speed control fg oscillator band gap 5-v step-down regulator sw vreg 3.3-v ldo 1.8-v ldo v3p3 v1p8 speed adc cppcpn vcp gnd i communication 2 c register eeprom gnd sda scl swgnd dir u v w charge pump pre- driver pre- driver pre- driver copyright ? 2017, texas instruments incorporated
17 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) step-down regulator with external inductor (buck mode) step-down regulator with external resistor (linear mode) figure 7. step-down regulator configurations 8.3.1.2 3.3-v and 1.8-v ldos the DRV10987 device includes a 3.3-v ldo and a 1.8-v ldo. the 1.8-v ldo is for internal circuits only. the 3.3-v ldo is mainly for internal circuits, but can also drive external loads not to exceed i v3p3_max . for example, it can work as a pullup voltage for the fg, dir, sda, and scl interfaces. both the v1p8 and v3p3 capacitors must be connected to gnd. 8.3.2 protection circuits 8.3.2.1 thermal shutdown the DRV10987 device has a built-in thermal shutdown function, which shuts down the device when the junction temperature is more than t sdn ? c and recovers operating conditions when the junction temperature falls to t sdn ? t sdn_hys ? c. the overtemp status bit (address 0x00, bit 15) is set during thermal shutdown. in addition to the thermal shutdown function, there is a warning bit that is set whenever the device exceeds t warn and is indicated by the tempwarning bit of the faultreg register (address 0x00, bit 14). 8.3.2.2 undervoltage lockout (uvlo) the DRV10987 device has a built-in uvlo function block. the device is locked out when v cc is below v uvlo_f and is unlocked when v cc is above v uvlo_r . the hysteresis of the uvlo threshold is v uvlo_hys . in addition to the main supply, the step-down regulator, charge pump, and 3.3-v ldo all have undervoltage lockout monitors. 8.3.2.3 overcurrent protection (ocp) the overcurrent shutdown function acts to protect the device if the current, as measured from the fets, exceeds the i oc-limit threshold. the overcurrent shutdown function protects the device in the event of a short-circuit condition on the motor phases. a short-circuit condition includes phase shorts to gnd, phase shorts to phase, or phase shorts to v cc . the DRV10987 device places the output drivers into a high-impedance state until the lock time t lock_off has expired. the overcurr status bit of the faultreg register (address 0x00, bit 11) is set. the DRV10987 device also provides software current-limit and lock-detection current-limit functions to protect the device and motor (see current limits and lock detect and fault handling ). load 39 vreg v cc sw swgnd 5 v ic 47 h 10 f vreg v cc sw swgnd 5 v ic 10 f
18 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) 8.3.2.4 lock when the motor is blocked or stopped by an external force, lock protection is triggered, and the device stops driving the motor immediately. after the lock release time t lock_off , the DRV10987 device resumes driving the motor again. if the lock condition is still present, it enters the next lock protection cycle, and repeats until the lock condition is removed. with this lock protection, the motor and device do not overheat or become damaged due to the motor being locked (see lock detect and fault handling ). during a lock condition the status register indicates which of the locks has occurred. 8.3.3 motor speed control the DRV10987 device offers four methods for indirectly controlling the speed of the motor by adjusting the output voltage amplitude. this can be accomplished by varying the supply voltage (v cc ) or by controlling the speed command. the speed command can be controlled in one of three ways. the user can set the speed command by adjusting either the pwm input (pwm in) or the analog input (analog) or by writing the speed command directly through the i 2 c serial port (i 2 c). the speed command is used to determine the pwm duty cycle output (pwm_dco) (see figure 9 ). the pwm input (pwm in) can have a minimum duty cycle limit applied. dutycyclelimit[1:0], accessible through the i 2 c interface, allows the user to configure the minimum duty cycle behavior. this behavior is illustrated in figure 8 . figure 8. duty cycle profile the speed command may not always be equal to the pwm_dco because the DRV10987 device has the avs function (see anti-voltage surge function ), the software current-limit function (see software current limit ), and the closed-loop accelerate function (see closed-loop accelerate ) to optimize the control performance. these functions can limit the pwm_dco, which affects the output amplitude (see figure 9 ). 5 10 input duty cycle 0 0 1.5 input duty cycle (%) output duty cycle (%) 100 dutycyclelimit[1:0], reg0x95 00 - linear down to 5%, then holds at 5% until duty command is 1.5 %; 0 % for duty command below 1.5 %. 01 - linear down to 10%, then holds at 10% until duty command is 1.5 %; 0 % for duty command below 1.5 %. 10 5 10 5 dutycyclelimit[1:0], reg0x95 10 - linear down to 5%, then holds at 5% until duty command is 1.5 %; 100 % for duty command below 1.5 %. 11 - linear down to 10%, then holds at 10% until duty command is 1.5 %; 100 % for duty command below 1.5 %. 0 1.5 input duty cycle (%) 10 5 output duty cycle (%) 0
19 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) figure 9. multiplexing the speed command to the output amplitude applied to the motor the output voltage amplitude applied to the motor is developed through sine wave modulation so that the phase- to-phase voltage is sinusoidal. when any phase is measured with respect to ground, the waveform is sinusoidally coupled with third-order harmonics. this encoding technique permits one phase to be held at ground while the other two phases are pulse-width modulated. figure 10 and figure 11 show the sinusoidal encoding technique used in the DRV10987 device. figure 10. pwm output and the average value sinusoidal voltage from phase to phase sinusoidal voltage with third-order harmonics from phase to gnd figure 11. representing sinusoidal voltages with third-order harmonic output the output amplitude is determined by the magnitude of v cc and the pwm duty cycle output (pwm_dco). the pwm_dco represents the peak duty cycle that is applied in one electrical cycle. the maximum amplitude is reached when pwm_dco is at 100%. the peak output amplitude is v cc . when the pwm_dco is at 50%, the peak amplitude is v cc / 2 (see figure 12 ). pwm in analog i 2 c pwm_ dco avs, acceleration current limit closed loop accelerate pwm duty adc speed command output amplitude motor v cc x speed pin copyright ? 2017, texas instruments incorporated pwm output average value u-v v-w w-u u v w
20 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) (1) see table 2 for details on pwm duty cycle requirements to exit sleep mode. (2) see required sequence to enter sleep mode for the required sequence to enter sleep mode. figure 12. output voltage amplitude adjustment motor speed is controlled indirectly by controlling the output amplitude, which is achieved by either controlling v cc , or controlling the pwm_dco. the DRV10987 device provides different options for the user to control the pwm_dco: ? analog input (speed pin) ? pwm encoded digital input (speed pin) ? i 2 c serial interface. see the closed loop section for more information. 8.3.4 overvoltage protection the recommended operation voltage of the DRV10987 device is from 6.2 v to 28 v. the device is able to drive the motor within this v cc range. if v cc goes higher than v ov_r , DRV10987 stops driving the motor and protects its own circuitry. when v cc drops below v ov_f , the DRV10987 device continues to operate the motor based on the user ? s command. the overvoltage protection works as long as the v cc slew rate is more than 10 v/ms. 8.3.5 sleep or standby condition the DRV10987 device is available in either a sleep mode (DRV10987d) or standby mode version (DRV10987s). the DRV10987 device enters either sleep or standby to conserve energy. when the device enters either sleep or standby, the device stops driving the motor. the step-down regulator is disabled in the sleep mode version to conserve more energy. the i 2 c interface is disabled and any register data not stored in eeprom is reset for the sleep mode version. the switching regulator remains active in the standby mode version. the register data is maintained, and the i 2 c interface remains active for standby mode version. for different speed command modes, table 1 shows the timing and command to enter the sleep or standby condition. table 1. conditions to enter or exit sleep or standby condition speed command mode enter sleep or standby condition exit from standby condition exit from sleep condition analog speed pin voltage < v en_sl_sb for t en_sl_sb speed pin voltage > v ex_sb for t ex_ sb speed pin high (v > v dig_ih ) for t ex_sl_sb pwm speed pin low (v < v dig_il ) for t en_sl_sb speed pin high (v > v dig_ih ) for t ex_sl_sb speed pin high (v > v dig_ih ) for t ex_sl_sb (1) i 2 c spdctrl[8:0] is programmed as 0 for t en_sl_sb (2) spdctrl[8:0] is programmed as non-zero for t ex_sl_sb speed pin high (v > v dig_ih ) for t ex_sl_sb v cc v / 2 cc 100% pwm dco 50% pwm dc0
21 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated note that when using the analog speed command, a higher voltage is required to exit from the sleep condition than from the standby condition. the i 2 c speed command cannot take the device out of the sleep condition because i 2 c communication is disabled during the sleep condition. table 2. minimum pwm duty cycle requirement for different pwm frequency to exit sleep condition input pwm frequency (khz) pwm duty cycle (%) 0.1 to 0.5 14 0.5 to 1 11 1 to 50 9 50 to 100 4 100 3.5 8.3.5.1 required sequence to enter sleep mode in i 2 c speed command mode, either of two sequence options can be used to enter sleep mode. 8.3.5.1.1 option 1 1. provide a non-zero value to the speed control register. for example, write 100 to register 0x30, speedctrl[8:0]. 2. set the i 2 c override bit to 1. that is, write 1 to register 0x30, speedctrl[15]. 3. be sure speed pin voltage is less than v en_sl_sb for t en_sl_sb . 4. provide the value of zero to the speed control register to enter sleep mode. that is, write 0 to register 0x30, speedctrl[8:0]. 8.3.5.1.2 option 2 1. set the motor disable bit to 1. that is, write 1 to register 0x60, eectrl[15]. 2. set the i 2 c override bit to 1. that is, write 1 to register 0x30, speedctrl[15]. 3. set the motor disable bit to 0. that is, write 0 to register 0x60, eectrl[15]. 4. provide the value of zero to the speed control register to enter sleep mode. that is, write 0 to register 0x30, speedctrl[8:0]. 8.3.6 eeprom access the DRV10987 device has 112 bits (7 registers with 16-bit width) of eeprom data, which are used to program the motor parameters as described in the i 2 c serial interface . the procedure for programming the eeprom is as follows. ti recommends to perform the eeprom programming without the motor spinning, cycle the power after the eeprom write, and read back the eeprom to verify the programming is successful. 1. power up with any voltage within operating voltage range (6.2 v to 28 v) 2. wait 10 ms 3. write register 0x60 to set mtr_dis = 1; this disables the motor driver. 4. write register 0x31 with 0x0000 to clear the eeprom access code 5. write register 0x31 with 0xc0de to enable access to eeprom 6. read register 0x32 for eereadystatus = 1 7. case-a: mass write a. write all individual shadow registers a. write register 0x90 (config1) with config1 data b. ... c. write register 0x96 (config7) with config7 data b. write the following to register 0x35 a. shadowregen = 0 b. eerefresh = 0
22 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated c. eewrnen = 1 d. eeprom access mode = 10 c. wait for register 0x32 eereadystatus = 1 ? eeprom is now updated with the contents of the shadow registers. 8. case-b: mass read a. write the following to register 0x35 a. shadowregen = 0 b. eerefresh = 0 c. eewrnen = 0 d. eeaccmode = 10 b. internally, the device starts reading the eeprom and storing it in the shadow registers. c. wait for register 0x32 eereadystatus = 1 ? shadow registers now contain the eeprom values 9. write register 0x60 to set mtr_dis = 0; this re-enables the motor driver
23 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.4 device functional modes this section includes the logic required to be able to reliably start and drive the motor. it describes the processes used in the logic core and provides the information needed to configure the parameters effectively to work over a wide range of applications. 8.4.1 motor parameters see the drv10983-q1 tuning guide for the motor parameter measurement. the motor phase resistance (r ph_ct ) and bemf constant (kt) are two important parameters used to characterize a bldc motor. the DRV10987 device requires these parameters to be configured in the register. the motor phase resistance is programmed by writing the values for rm[6:0] (combination of rmshift[2:0] and rmvalue[3:0]) in the config1 register. the bemf constant is programmed by writing the values for kt[6:0] (combination of ktshift[2:0] and ktvalue[3:0]) in the config2 register. 8.4.1.1 motor phase resistance (r ph_ct ) for a wye-connected motor, the motor phase resistance refers to the resistance from the phase output to the center tap, r ph_ct (denoted as r ph_ct in figure 13 ). figure 13. wye-connected motor resistance for a delta-connected motor, the motor phase resistance refers to the equivalent phase to center tap in the wye configuration. in figure 14 , it is denoted as r y . r ph_ct = r y . for both the delta-connected motor and the wye-connected motor, the easy way to get the equivalent r ph_ct is to measure the resistance between two phase terminals (r ph_ph ), and then divide this value by two, r ph_ct = ? r ph_ph . figure 14. delta-connected motor and the equivalent wye connections phase u phase v phase w center tap r y r y r y r ? r ? r ? phase u phase v phase w center tap r ph_ct r ph_ct r ph_ct
24 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) the motor phase resistance (r ph_ct ) must be converted to a 7-bit digital register value rm[6:0] to program the motor phase resistance value. the digital register value can be determined as follows: 1. convert the motor phase resistance (r ph_ct ) to a digital value where the lsb is weighted to represent 9.67 m : rmdig = r ph_ct / 0.00967. 2. encode the digital value such that rmdig = rmvalue[3:0] < < rmshift[2:0]. the maximum resistor value, r ph_ct , that can be programmed for the DRV10987 device is 18.5 , which represents rmdig = 1920 and an encoded rm[6:0] value of 0x7fh. the minimum resistor the DRV10987 device supports is 0.029 , r ph_ct , which represents rmdig = 3. for convenience, the encoded value for rm[6:0] can also be obtained from table 3 . table 3. motor phase resistance look-up table rm[6:0] {rmshift[2:0], rmvalue[3:0]} r ph_ct ( ) rm[6:0] {rmshift[2:0], rmvalue[3:0]} r ph_ct ( ) rm[6:0] {rmshift[2:0], rmvalue[3:0]} r ph_ct ( ) binary hex binary hex binary hex 000 0000 0x00 0 0101000 0x28 0.3104 1011000 0x58 2.4832 000 0001 0x01 0.0097 010 1001 0x29 0.3492 101 1001 0x59 2.7936 000 0010 0x02 0.0194 010 1010 0x2a 0.388 101 1010 0x5a 3.104 000 0011 0x03 0.0291 010 1011 0x2b 0.4268 101 1011 0x5b 3.4144 000 0100 0x04 0.0388 010 1100 0x2c 0.4656 101 1100 0x5c 3.7248 000 0101 0x05 0.0485 010 1101 0x2d 0.5044 101 1101 0x5d 4.0352 000 0110 0x06 0.0582 010 1110 0x2e 0.5432 101 1110 0x5e 4.3456 000 0111 0x07 0.0679 010 1111 0x2f 0.582 101 1111 0x5f 4.656 000 1000 0x08 0.0776 011 1000 0x38 0.6208 110 1000 0x68 4.9664 000 1001 0x09 0.0873 011 1001 0x39 0.6984 110 1001 0x69 5.5872 000 1010 0x0a 0.097 011 1010 0x3a 0.776 110 1010 0x6a 6.208 000 1011 0x0b 0.1067 011 1011 0x3b 0.8536 110 1011 0x6b 6.8288 000 1100 0x0c 0.1164 011 1100 0x3c 0.9312 110 1100 0x6c 7.4496 000 1101 0x0d 0.1261 011 1101 0x3d 1.0088 110 1101 0x6d 8.0704 000 1110 0x0e 0.1358 011 1110 0x3e 1.0864 110 1110 0x6e 8.6912 000 1111 0x0f 0.1455 011 1111 0x3f 1.164 110 1111 0x6f 9.312 001 1000 0x18 0.1552 100 1000 0x48 1.2416 111 1000 0x78 9.9328 001 1001 0x19 0.1746 100 1001 0x49 1.3968 111 1001 0x79 11.1744 001 1010 0x1a 0.194 100 1010 0x4a 1.552 111 1010 0x7a 12.416 001 1011 0x1b 0.2134 100 1011 0x4b 1.7072 111 1011 0x7b 13.6576 001 1100 0x1c 0.2328 100 1100 0x4c 1.8624 111 1100 0x7c 14.8992 001 1101 0x1d 0.2522 100 1101 0x4d 2.0176 111 1101 0x7d 16.1408 001 1110 0x1e 0.2716 100 1110 0x4e 2.1728 111 1110 0x7e 17.3824 001 1111 0x1f 0.291 100 1111 0x4f 2.328 111 1111 0x7f 18.624
25 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.4.1.2 bemf constant (kt) the bemf constant, kt[6:0], describes the phase-to-phase bemf voltage of the motor as a function of the motor velocity. figure 15 shows the measurement technique for this constant as used in the DRV10987 device. figure 15. kt ph definition with the motor coasting, use an oscilloscope to capture the differential voltage waveform between any two phases. derive the motor bemf constant used by the DRV10987 device as shown in equation 1 . kt ph = e p t e where ? e p is ? the peak-to-peak amplitude of the measured voltage ? t e is the electrical period (1) the measured bemf constant (kt ph ) must be converted to a 7-bit digital register value kt[6:0] (combination of ktshift[2:0] and ktvalue[3:0]) to program the bemf constant value. the digital register value can be determined as follows: 1. convert the measured kt ph to a weighted digital value: kt ph_dig = 1090 kt ph 2. encode the digital value such that kt ph_dig = ktvalue[3:0] < < ktshift[2:0]. the maximum kt ph that can be programmed is 1760 mv/hz. this represents a digital value of 1920 and an encoded kt[6:0] value of 0x7fh. the minimum kt ph that can be programmed is 0.92 mv/hz, which represents a digital value of 1 and an encoded kt[6:0] value of 0x01h. for convenience, the encoded value of kt[6:0] may also be obtained from table 4 . rm lm rm lm rm lm phv phw phu eu ev ew e p t e p p e e e e kt 1 f t = =
26 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated table 4. bemf constant (kt) look-up table kt[6:0] {ktshift[2:0], ktvalue[3:0]} kt ph (mv/hz) kt [6:0] {ktshift[2:0], ktvalue[3:0]} kt ph (mv/hz) kt [6:0] {ktshift[2:0], ktvalue[3:0]} kt ph (mv/hz) binary hex binary hex binary hex 000 0000 0x00 0 010 1000 0x28 29.44 101 1000 0x58 235.52 000 0001 0x01 0.92 010 1000 0x29 33.12 101 1000 0x59 264.96 000 0010 0x02 1.84 010 1000 0x2a 36.8 101 1000 0x5a 294.4 000 0011 0x03 2.76 010 1000 0x2b 40.48 101 1000 0x5b 323.84 000 0100 0x04 3.68 010 1000 0x2c 44.16 101 1000 0x5c 353.28 000 0101 0x05 4.6 010 1000 0x2d 47.84 101 1000 0x5d 382.72 000 0110 0x06 5.52 010 1000 0x2e 51.52 101 1000 0x5e 412.16 000 0111 0x07 6.44 010 1000 0x2f 55.2 101 1000 0x5f 441.6 000 1000 0x08 7.36 011 1000 0x38 58.88 110 1000 0x68 471.04 000 1001 0x09 8.28 011 1000 0x39 66.24 110 1000 0x69 529.92 000 1010 0x0a 9.2 011 1000 0x3a 73.6 110 1000 0x6a 588.8 000 1011 0x0b 10.12 011 1000 0x3b 80.96 110 1000 0x6b 647.68 000 1100 0x0c 11.04 011 1000 0x3c 88.32 110 1000 0x6c 706.56 000 1101 0x0d 11.96 011 1000 0x3d 95.68 110 1000 0x6d 765.44 000 1110 0x0e 12.88 011 1000 0x3e 103.04 110 1000 0x6e 824.32 000 1111 0x0f 13.8 011 1000 0x3f 110.4 110 1000 0x6f 883.2 001 1000 0x18 14.72 100 1000 0x48 117.76 111 1000 0x78 942.08 001 1001 0x19 16.56 100 1000 0x49 132.48 111 1000 0x79 1059.84 001 1010 0x1a 18.4 100 1000 0x4a 147.2 111 1000 0x7a 1177.6 001 1011 0x1b 20.24 100 1000 0x4b 161.92 111 1000 0x7b 1295.36 001 1100 0x1c 22.08 100 1000 0x4c 176.64 111 1000 0x7c 1413.12 001 1101 0x1d 23.92 100 1000 0x4d 191.36 111 1000 0x7d 1530.88 001 1110 0x1e 25.76 100 1000 0x4e 206.08 111 1000 0x7e 1648.64 001 1111 0x1f 27.6 100 1000 0x4f 220.8 111 1000 0x7f 1766.4 8.4.2 starting the motor under different initial conditions the motor can be in one of three states when the DRV10987 device attempts to begin the start-up process. the motor may be stationary, or spinning in the forward or reverse directions. the DRV10987 device includes a number of features to allow for reliable motor start under all of these conditions. figure 16 shows the motor start- up flow for each of the three initial motor states. 8.4.2.1 case 1 ? motor is stationary if the motor is stationary, the commutation logic must be initialized to be in phase with the position of the motor. the DRV10987 device provides for two options to initialize the commutation logic to the motor position. initial position detect (ipd) determines the position of the motor based on the deterministic inductance variation, which is often present in bldc motors. the align-and-go technique forces the motor into alignment by applying a voltage across a particular motor phase to force the motor to rotate in alignment with this phase. 8.4.2.2 case 2 ? motor is spinning in the forward direction if the motor is spinning forward with enough velocity, the DRV10987 device may be configured to go directly into closed loop. by resynchronizing to the spinning motor, the user achieves the fastest possible start-up time for this initial condition. 8.4.2.3 case 3 ? motor is spinning in the reverse direction if the motor is spinning in the reverse direction, the DRV10987 device provides several methods to convert it back to the forward direction.
27 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated one method, reverse drive, allows the motor to be driven so that it accelerates through zero velocity. the motor achieves the shortest possible spin-up time in systems where the motor is spinning in the reverse direction. if this feature is not selected, then the DRV10987 device may be configured either to wait for the motor to stop spinning or to brake the motor. after the motor has stopped spinning, the motor start-up sequence proceeds as it would for a motor which is stationary. take care when using the reverse-drive or brake feature to ensure that the current is limited to an acceptable level and that the supply voltage does not surge as a result of energy being returned to the power supply. figure 16. start the motor under different initial conditions stationary spinning forward spinning reversely ipd align and go direct closed loop wait brake reverse drive
28 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.4.3 motor start sequence figure 17 shows the motor-start sequence implemented in the DRV10987 device. figure 17. motor starting-up flow accelerate state the DRV10987 device accelerates the motor according to the settings of staccel and staccel2. after applying the accelerate settings, the mss advances to the speed > op2clsthr judgment. align state the DRV10987 device performs the align function (see align ). after the align completes, the mss transitions to the accelerate state. brake state the device performs the brake function (see motor brake ). brken judgment the mss checks to determine whether the brake function is enabled (brkdonethr[2:0] 000). if the brake function is enabled, the mss advances to the brake state. closedloop state in this state, the DRV10987 device drives the motor based on feedback from the commutation control algorithm. dir pin change judgment if the dir pin is changed during any of above states, DRV10987 device stops driving the motor and restarts from the beginning. forward judgment the mss determines whether the motor is spinning in the forward or the reverse direction. if the motor is spinning in the forward direction, the DRV10987 device executes the power on isden isd n y y forward closedloop n y n brken rvsdren y n n rvsdr align ipd accelerate ipden n y n y n y y n brake y motor resynchronization dir pin change speed > rvsdrthr speed > op2cisthr time > brkdonethr speed < isdthr
29 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated resynchronization (see motor resynchronization ) process by transitioning directly into the closedloop state. if the motor is spinning in the reverse direction, the mss proceeds to the speed > rvsdrthr. ipden judgment the mss checks to see if ipd has been enabled (ipdcurrthr[3:0] 0000). if the ipd is enabled, the mss transitions to the ipd state. otherwise, it transitions to the align state. ipd state the DRV10987 device performs the ipd function. the ipd function is described in initial position detect (ipd) . after the ipd completes, the mss transitions to the accelerate state. isd state the mss determines the initial condition of the motor (see initial speed detect (isd) ). isden judgment after power-on, the DRV10987 mss enters the isden judgment where it checks to see if the initial speed detect (isd) function is enabled (isden = 1). if isd is disabled, the mss proceeds directly to the brken judgment. if isd is enabled, the motor start sequence advances to the isd state. power-on state this is the initial power-on state of the motor start sequencer (mss). the mss starts in this state on initial power-up or whenever the DRV10987 device comes out of standby mode. rvsdren judgment the mss checks to see if the reverse drive function is enabled (rvsdren = 1). if it is, the mss transitions into the rvsdr state. if the reverse drive function is not enabled, the mss advances to the brken judgment. rvsdr state the DRV10987 device drives the motor in the forward direction to force it to rapidly decelerate (see reverse drive ). when it reaches zero velocity, the mss transitions to the accelerate state. speed < isdthr judgment if the motor speed is lower than the threshold defined by isdthr[1:0], then the motor is considered to be stationary and the mss proceeds to the brken judgment. if the speed is greater than the threshold defined by isdthr[1:0], the start sequence proceeds to the forward judgment. speed > op2clsthr judgment the motor accelerates until the drive rate exceeds the threshold configured by the op2clsthr[4:0] settings. when this threshold is reached, the DRV10987 device enters into the closedloop state. speed > rvsdrthr judgment the motor start sequencer checks to see if the reverse speed is greater than the threshold defined by rvsdrthr[1:0]. if it is, then the mss returns to the isd state to allow the motor to decelerate. this prevents the DRV10987 device from attempting to reverse drive or brake a motor that is spinning too quickly. if the reverse speed of the motor is less than the threshold defined by rvsdrthr[1:0], then the mss advances to the rvsdren judgment. time > brkdonethr judgment the mss applies brake for a time configured by brkdonethr[2:0]. after brake state, the mss advances to the ipden judgment. 8.4.3.1 initial speed detect (isd) the isd function is used to identify the initial condition of the motor. if the function is disabled, the DRV10987 device does not perform the initial speed detect function and treats the motor as if it is stationary. phase-to-phase comparators are used to detect the zero crossings of the motor bemf voltage while it is coasting (motor phase outputs are in the high-impedance state). figure 18 shows the configuration of the comparators.
30 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 18. initial speed detect function if the uw comparator output is lagging the uv comparator by 60 , the motor is spinning forward. if the uw comparator output is leading the uv comparator by 60 , the motor is spinning in reverse. the motor speed is determined by measuring the time between two rising edges of either of the comparators. if neither of the comparator outputs toggles for a given amount of time, the condition is defined as stationary. the amount of time can be programmed by setting the register bits isdthr[1:0]. 8.4.3.2 motor resynchronization the resynchronize function works when the isd function is enabled and determines that the initial state of the motor is spinning in the forward direction. the speed and position information measured during isd are used to initialize the drive state of the DRV10987 device, which can transition directly into the closed-loop running state without needing to stop the motor. 8.4.3.3 reverse drive the isd function measures the initial speed and the initial position; the DRV10987 reverse drive function acts to reverse accelerate the motor through zero speed and to continue accelerating until the closed loop threshold is reached (see figure 19 ). if the reverse speed is greater than the threshold configured in rvsdrthr[1:0], then the DRV10987 device waits until the motor coasts to a speed that is less than the threshold before driving the motor to reverse accelerate. figure 19. reverse drive function u v w 60 degrees ++ time speed closed loop reverse drive op2clsthr open loop revdrthr coasting
31 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated reverse drive is suitable for applications where the load condition is light at low speed and relatively constant and where the reverse speed is low (for example, a fan motor with little friction). for other load conditions, the motor brake function provides a method for helping force a motor which is spinning in the reverse direction to stop spinning before the device initiates a normal start-up sequence. 8.4.3.4 motor brake the motor brake function can be used to stop the spinning motor before attempting to start the motor. the brake is applied by turning on all three of the low-side driver fets. brake is enabled by configuring a non-zero brkdonethr[2:0]. the driver comes out of the brake state only when the phase current is lower than brkcurthrsel for brkdonethr[2:0] time. after the motor is stopped, the motor position is unknown. to proceed with restarting in the correct direction, the ipd or align-and-go algorithm must be implemented. the motor start sequence is the same as it would be for a motor starting in the stationary condition. the driver enters the brake state before entering the ipd or align-and-go state. the motor brake function can be disabled, in which case the DRV10987 device skips the brake state and attempts to spin the motor as if it were stationary. if this happens while the motor is spinning in either direction, the start-up sequence may not be successful. 8.4.3.5 motor initialization 8.4.3.5.1 align the DRV10987 device aligns a motor by injecting dc current through a particular phase pattern which is current flowing into phase v, flowing out from phase w for a certain time (configured by aligntime[2:0]). the current magnitude is determined by openlcurr[1:0]. the motor should be aligned at the known position. the time of align affects the start-up timing (see start-up timing ). a bigger-inertia motor requires longer align time. 8.4.3.5.2 initial position detect (ipd) the inductive sense method is used to determine the initial position of the motor when ipd is enabled. ipd is enabled by selecting ipdcurrthr[3:0] to any value other than 0000. ipd can be used in applications where reverse rotation of the motor is unacceptable. because ipd is not required to wait for the motor to align with the commutation, it can allow for a faster motor start sequence. ipd works well when the inductance of the motor varies as a function of position. because it works by pulsing current to the motor, it can generate acoustics which must be taken into account when determining the best start method for a particular application. 8.4.3.5.2.1 ipd operation ipd operates by sequentially applying voltage across two of the three motor phases according to the following sequence: vw wv uv vu wu uw (see figure 20 ). when the current reaches the threshold configured in ipdcurrthr[3:0], the voltage across the motor is stopped. the DRV10987 device measures the time it takes from when the voltage is applied until the current threshold is reached. the time varies as a function of the inductance in the motor windings. the state with the shortest time represents the state with the minimum inductance. the minimum inductance is because of the alignment of the north pole of the motor with this particular driving state.
32 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 20. ipd function 8.4.3.5.2.2 ipd release mode two options are available for stopping the voltage applied to the motor when the current threshold is reached. if ipdrlsmd = 0, the recirculate mode is selected. the low-side (s6) mosfet remains on to allow the current to recirculate between the mosfet (s6) and body diode (s2) (see figure 21 ). if ipdrlsmd = 1, the high- impedance mode is selected. both the high-side (s1) and low-side (s6) mosfets are turned off and the current flies back across the body diodes into the power supply (see figure 22 ). in the high-impedance state, the phase current has a faster settle-down time, but that could result in a surge on v cc . manage this with appropriate selection of either a clamp circuit or by providing sufficient capacitance between v cc and gnd. if the voltage surge cannot be contained and if it is unacceptable for the application, then select the recirculate mode. when selecting the recirculate mode, select the ipdclk[1:0] bits to give the current in the motor windings enough time to decay to 0. figure 21. ipd release mode 0 driving s1s2 u1 s3s4 s5s6 m s1s2 u1 s3s4 s5s6 brake (recirculate) m clock ipdclk drive v w w v u v v u w u u w current search the minimum time ipdcurrthr minimum time permanent magnet position saturation position of the magnetic field smallest inductance n s u v w
33 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 22. ipd release mode 1 8.4.3.5.2.3 ipd advance angle after the initial position is detected, the DRV10987 device begins driving the motor at an angle specified by ipdadvcagl[1:0]. advancing the drive angle anywhere from 0 to 180 results in positive torque. advancing the drive angle by 90 results in maximum initial torque. applying maximum initial torque could result in uneven acceleration to the rotor. select the ipdadvcagl[1:0] to allow for smooth acceleration in the application (see figure 23 ). figure 23. ipd advance angle 8.4.3.5.3 motor start after it is determined that the motor is stationary and after completing the motor initialization with either align or ipd, the DRV10987 device begins to accelerate the motor. this acceleration is accomplished by applying a voltage determined by the open-loop current setting (openlcurr[1:0]) to the appropriate drive state and by increasing the rate of commutation without regard to the real position of the motor (referred to as open-loop operation). the function of the open-loop operation is to drive the motor to a minimum speed so that the motor generates sufficient bemf to allow the commutation control logic to accurately drive the motor. table 5 lists the configuration options that can be set in the register to optimize the initial motor acceleration stage for different applications. n s u v w motor spinning direction ?dgydqfh ? advance ?dgydqfh ?dgydqfh n s u v w n s u v w n s u v w n s u v w s1s2 u1 s3s4 s5s6 s1s2 u1 s3s4 s5s6 m m driving hi-z (high-impedance)
34 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated table 5. configuration options for controlling open-loop motor start description reg. name configuration bits min. value max. value open- to closed-loop threshold config4 op2clsthr[4:0] 0.8 hz 204.8 hz align time config4 aligntime[2:0] 40 ms 5.3 s first-order acceleration coefficient config4 staccel[2:0] 0.019 hz/s 76 hz/s second-order acceleration coefficient config4 staccel2[2:0] 0.0026 hz/s 2 57 hz/s 2 open-loop current setting config3 openlcurr[1:0] 200 ma 1.6 a align current setting 150 ma 1.2 a open-loop current ramping config3 oplcurrrt[2:0] 0.023 v cc /s 6 v cc /s 8.4.3.6 start-up timing start-up timing is determined by the align and accelerate time. the align time can be set by aligntime[2:0]. the accelerate time is defined by the open-loop to closed-loop threshold op2clsthr[4:0] along with the first-order acceleration coefficient staccel[2:0](a1) and second-order acceleration coefficient staccel2[2:0](a2) accelerate rates. figure 24 shows the motor start-up process. figure 24. motor start-up process select the first-order and second-order acceleration coefficients to allow the motor to reliably accelerate from zero velocity up to the closed-loop threshold in the shortest time possible. using slow acceleration coefficients for open loop stage can help improve reliability in applications where it is difficult to initialize the motor accurately with either align or ipd. select the open- to closed-loop threshold to allow the motor to accelerate to a speed that generates sufficient bemf for closed-loop control. this is determined by the bemf constant of the motor based on the relationship described in equation 2 . bemf = kt ph speed (hz) (2) 8.4.4 align current during the align state, the measured align current is dependent on the actual motor phase resistance and r ds(on) of the internal fets. the relationship between measured align current and configured align current is derived from the actual motor phase resistance, configured motor phase resistance, and r ds(on) . where ? aligncurrent_measured is the actual align current measured during the align state ? aligncurrent_configured is the align current configured by openlcurr[1:0] ? r motor is the actual motor phase resistance ? r ds(on) is the resistance between the drain and source of the fets during the on-state ? r m is configured by rm[6:0] (3) m motor ds(on) r aligncurrent _ measured aligncurrent _ configured r r = + ? ? time speed close loop op2clsthr aligntime accelerate time accelerate time is determined by op2clsthr and a1, a2. speed = t + 0.5 t a1 a2 2
35 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.4.5 start-up current setting the start-up current setting is to control the peak start-up current during open loop. during open-loop operation, it is desirable to control the magnitude of drive current applied to the motor. this is helpful in controlling and optimizing the rate of acceleration. the limit takes effect during reverse drive, align, and acceleration. the start current is set by programming the openlcurr[1:0] bits. the current should be selected to allow the motor to reliably accelerate to the handoff threshold. heavier loads may require a higher current setting, but it should be noted that the rate of acceleration is limited by the acceleration rate (staccel[2:0], staccel2[2:0]). if the motor is started with more current than necessary to reliably reach the handoff threshold, it results in higher power consumption. the start current is controlled based on the relationship shown in equation 4 and figure 25 . the duty cycle applied to the motor is derived from the calculated value for u limit and the magnitude of the supply voltage, v cc , as well as the drive state of the motor. where ? i limit is configured by openlcurr[1:0] ? rm is configured by rm[6:0] ? speed is variable based the open-loop acceleration profile of the motor ? kt is configured by kt[6:0] (4) figure 25. motor start-up current 8.4.5.1 start-up current ramp-up a fast change in the applied drive current may result in a sudden change in the driving torque. in some applications, this could result in acoustic noise. to avoid this, the DRV10987 device allows the option of limiting the rate at which the current is applied to the motor. oplcurrrt[2:0] sets the maximum voltage ramp-up rate that is applied to the motor. the waveforms in figure 26 show how this feature can be used to gradually ramp the current applied to the motor. start driving with fast current ramp start driving with slow current ramp figure 26. motor start-up current ramp 8.4.6 closed loop in closed loop operation, the DRV10987 device continuously samples the current in the u phase of the motor and uses this information to estimate the bemf voltage that is present. the drive state of the motor is controlled based on the estimated bemf voltage. limit limit u i rm speed hz kt u u bemf = kt speed rm v = bemf + i rm u m copyright ? 2017, texas instruments incorporated
36 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.4.6.1 half-cycle control and full-cycle control the estimated bemf used to control the drive state of the motor has two zero-crosses every electrical cycle. the DRV10987 device can be configured to update the drive state either once every electrical cycle or twice for every electrical cycle. when adjmode is programmed to 1, half-cycle adjustment is applied. the control logic is triggered at both the rising edge and falling edge. when adjmode is programmed to 0, full-cycle adjustment is applied. the control logic is triggered only at the rising edge (see figure 27 ). half-cycle adjustment provides a faster response when compared with full-cycle adjustment. use half-cycle adjustment whenever the application requires operation over large dynamic loading conditions. use the full-cycle adjustment for low-current ( < 1 a) applications because it offers more tolerance for current-measurement offset errors. figure 27. closed-loop control commutation-adjustment mode 8.4.6.2 analog-mode speed control the speed input pin can be configured to operate as an analog input (spdctrlmd = 0). when configured for analog mode, the voltage range on the speed pin can be varied from 0 to v3p3. if speed > v ana_fs , the speed command is maximum. if v ana_zs speed < v ana_fs the speed command changes linearly according to the magnitude of the voltage applied at the speed pin. if speed < v ana_zs the speed command is to stop the motor. figure 28 shows the speed command when operating in analog mode. figure 28. analog-mode speed command 8.4.6.3 digital pwm-input-mode speed control if spdctrlmd = 1, the speed input pin is configured to operate as a pwm-encoded digital input. the pwm duty cycle applied to the speed pin can be varied from 0 to 100%. the speed command is proportional to the pwm input duty cycle. the speed command stops the motor when the pwm input keeps at 0 for t en_sl_sb (see figure 29 ). the frequency of the pwm input signal applied to the speed pin is defined as f pwm . this is the frequency the device can accept to control motor speed. it does not correspond to the pwm output frequency that is applied to the motor phase. the pwm output frequency can be configured to be either 25 khz when the pwmfreq bit is set to 0 or to 50 khz when pwmfreq bit is set to 1. speed command analog input maximum speed command v ana-zs v ana-fs adjustment (half cycle) zero cross signal adjustment (full cycle) zero cross signal estimated position real driving voltage real position ideal driving voltage estimated position real driving voltage real position ideal driving voltage
37 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 29. pwm-mode speed command 8.4.6.4 i 2 c-mode speed control the DRV10987 device can also command the speed through the i 2 c serial interface. to enable this feature, the override bit is set to 1. when the DRV10987 device is configured to operate in i 2 c mode, it ignores the signal applied to the speed pin. the speed command can be set by writing the spdctrl[8:0] bits. the 9-bit spdctrl [8:0] located in the speedctrl registers is used to set the peak amplitude voltage applied to the motor. the maximum speed command is set when spdctrl [8:0] is set to 0x1ff (511). 8.4.6.5 closed-loop accelerate to prevent sudden changes in the torque applied to the motor which could result in acoustic noise, the DRV10987 device provides the option of limiting the maximum rate at which the speed command changes. clslpaccel[2:0] can be programmed to set the maximum rate at which the speed command changes (shown in figure 30 ). figure 30. closed-loop accelerate 8.4.6.6 control coefficient the DRV10987 device continuously measures the motor current and uses this information to control the drive state of the motor when operating in closed-loop mode. in applications where noise makes it difficult to control the commutation optimally, the ctrlcoef[1:0] can be used to attenuate the feedback used for closed-loop control. the loop is less reactive to the noise on the feedback and provides for a smoother output. 8.4.6.7 commutation control to achieve the best efficiency, it is often desirable to control the drive state of the motor so that the motor phase current is aligned with the motor bemf voltage. to align the motor phase current with the motor bemf voltage, consider the inductive effect of the motor. the voltage applied to the motor should be applied in advance of the motor bemf voltage (see figure 31 ). the DRV10987 device provides configuration bits for controlling the time (t adv ) between the driving voltage and bemf. speed command input speed command after closed loop accelerate buffer closed loop accelerate settings x% y% x% y% speed command pwm duty maximum speed command 100% 0
38 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated for motors with salient pole structures, aligning the motor bemf voltage with the motor current may not achieve the best efficiency. in these applications, the timing advance should be adjusted accordingly. accomplish this by operating the system at constant speed and load conditions and by adjusting t adv until the minimum current is achieved. figure 31. advance time (t adv ) definition the DRV10987 device has two options for adjusting the motor commutate advance time. when commadvmode = 0, mode 0 is selected. when commadvmode = 1, mode 1 is selected. mode 0: t adv is maintained to be a fixed time relative to the estimated bemf zero cross as determined by equation 5 . t adv = t setting (5) mode 1: t adv is maintained to be a variable time relative to the estimated bemf zero cross as determined by equation 6 . t adv = t setting (v u ? bemf) / v u . where ? v u is the phase voltage amplitude ? bemf is the phase bemf amplitude (6) t setting (in s) is determined by the configuration of the tctrladvshift [2:0] and tctrladvvalue [3:0] bits as defined in equation 7 . for convenience, the available t setting values are provided in table 6 . t setting = 2.5 s [tctrladvvalue[3:0]] < < tctrladvshift[2:0] (7) phase voltage phase current phase bemf t adv
39 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated table 6. configuring commutation advance timing by adjusting t setting tctrladv [6:0] {tctrladvshift[2:0], tctrladvvalue[3:0]} t setting ( s) tctrladv [6:0] {tctrladvshift[2:0], tctrladvvalue[3:0]} t setting ( s) tctrladv [6:0] {tctrladvshift[2:0], tctrladvvalue[3:0]} t setting ( s) binary hex binary hex binary hex 000 0000 0x00 0 010 1000 0x28 80 101 1000 0x58 640 000 0001 0x01 2.5 010 1001 0x29 90 101 1001 0x59 720 000 0010 0x02 5 010 1010 0x2a 100 101 1010 0x5a 800 000 0011 0x03 7.5 010 1011 0x2b 110 101 1011 0x5b 880 000 0100 0x04 10 010 1100 0x2c 120 101 1100 0x5c 960 000 0101 0x05 12.5 010 1101 0x2d 130 101 1101 0x5d 1040 000 0110 0x06 15 010 1110 0x2e 140 101 1110 0x5e 1120 000 0111 0x07 17.5 010 1111 0x2f 150 101 1111 0x5f 1200 000 1000 0x08 20 011 1000 0x38 160 110 1000 0x68 1280 000 1001 0x09 22.5 011 1001 0x39 170 110 1001 0x69 1440 000 1010 0x0a 25 011 1010 0x3a 200 110 1010 0x6a 1600 000 1011 0x0b 27.5 011 1011 0x3b 220 110 1011 0x6b 1760 000 1100 0x0c 30 011 1100 0x3c 240 110 1100 0x6c 1920 000 1101 0x0d 32.5 011 1101 0x3d 260 110 1101 0x6d 2080 000 1110 0x0e 35 011 1110 0x3e 280 110 1110 0x6e 2240 000 1111 0x0f 37.5 011 1111 0x3f 300 110 1111 0x6f 2400 001 1000 0x18 40 100 1000 0x48 320 111 1000 0x78 2560 001 1001 0x19 45 100 1001 0x49 360 111 1001 0x79 2880 001 1010 0x1a 50 100 1010 0x4a 400 111 1010 0x7a 3200 001 1011 0x1b 55 100 1011 0x4b 440 111 1011 0x7b 3520 001 1100 0x1c 60 100 1100 0x4c 480 111 1100 0x7c 3840 001 1101 0x1d 65 100 1101 0x4d 520 111 1101 0x7d 4160 001 1110 0x1e 70 100 1110 0x4e 560 111 1110 0x7e 4480 001 1111 0x1f 75 100 1111 0x4f 600 111 1111 0x7f 4800 8.4.7 current limits the DRV10987 device has several current-limit modes to help ensure optimal control of the motor and to ensure safe operation. the various current-limit modes are listed in table 7 . software current limit is used to provide a means of controlling the amount of current delivered to the motor. this is useful when the system must limit the amount of current pulled from the power supply during motor start-up. the lock-detection current limit is a configurable threshold that can be used to limit the current applied to the motor. overcurrent protection is used to protect the device; therefore, it cannot be disabled or configured to a different threshold. the current-limit modes are described in the following sections. table 7. DRV10987 current-limit modes current limit mode situation action fault diagnosis software current limit motor start limit the output voltage amplitude no fault lock0: lock-detection current limit triggered motor locked stop driving the motor and enter the lock state mechanical rotation error overcurrent protection (ocp) short circuit stop driving the motor and enter the lock state circuit connection 8.4.7.1 software current limit the software current limit limits the voltage applied to the motor to prevent the current from exceeding the programmed threshold. the software current limit threshold is configured by writing the swilimitthr[3:0] bits to select i limit . the software current limit does not use a direct measurement of current. it uses the programmed motor phase resistance, rm, and programmed bemf constant (kt) to limit the voltage, v u , applied to the motor as shown in figure 32 and equation 8 .
40 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated when the software current limit is active, it does not stop the motor from spinning nor does it trigger a fault. the functionality of the software current limit is only available in closed-loop control. figure 32. software current limit v u_limit = i limit rm + speed kt (8) 8.4.8 lock detect and fault handling the DRV10987 device provides several options for determining if the motor becomes locked as a result of some external torque. five lock-detect schemes work together to ensure the lock condition is detected quickly and reliably. figure 33 shows the logic which integrates the various lock-detect schemes. when a lock condition is detected, the DRV10987 device takes action to prevent continuously driving the motor in order to prevent damage to the system or the motor. in addition to detecting if there is a locked motor condition, the DRV10987 device also identifies and takes action if there is no motor connected to the system. each of the five lock-detect schemes and the no-motor detection can be disabled by their respective register bits, locken[5:0]. when a lock condition is detected, the faultreg register provides an indication of which of the six different conditions was detected on lock5 to lock0. these bits are reset when the motor restarts. the bits in the faultreg register are set even if the lock detect scheme is disabled. the DRV10987 device reacts to either locked-rotor or no-motor-connected conditions by putting the output drivers into a high-impedance state. to prevent the energy in the motor from pumping the supply voltage, the DRV10987 device incorporates an anti-voltage-surge (avs) process whenever the output stages transition into the high-impedance state. the avs function is described in anti-voltage surge function . after entering the high- impedance state as a result of a fault condition, the system tries to restart after t lock_off . figure 33. lock detect and fault diagnosis lock-detection current limit speed abnormal open-loop stuck closed-loop stuck no-motor fault locken (0, 1, 2, 3, 4, 5) hi-z and restart logic or register: faultcode [5:0] set reset bemf abnormal copyright ? 2017, texas instruments incorporated i limit v u_limit rm m bemf = kt speed copyright ? 2017, texas instruments incorporated
41 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.4.8.1 lock0: lock-detection current limit triggered the lock-detection current-limit function provides a configurable threshold for limiting the current to prevent damage to the system. this is often tripped in the event of a sudden locked-rotor condition. the DRV10987 device continuously monitors the current in the low-side drivers as shown in figure 34 . if the current goes higher than the threshold configured by the hwilimitthr[2:0] bits, then the DRV10987 device stops driving the motor by placing the output phases into a high-impedance state. the lock0 bit is set and a lock condition is reported. the device retries after t lock_off . set the lock-detection current limit to a higher value than the software current limit. figure 34. lock-detection current limit 8.4.8.2 lock1: abnormal speed if the motor is operating normally, the motor bemf should always be less than the output amplitude. the DRV10987 device uses two methods of monitoring the bemf in the system. the u phase current is monitored to maintain an estimate of bemf based on the setting for rm[6:0] {rmshift[2:0],rmvalue[3:0]}. in addition, the bemf is estimated based on the operation speed of the motor and the setting for kt[6:0] {ktshift[2:0],ktvalue[3:0]}. figure 35 shows the method for using this information to detect a lock condition. if the motor bemf is much higher than the output amplitude for a certain period of time, t lck_etr , it means the estimated speed is wrong, and the motor has gotten out of phase. figure 35. lock detection 1 8.4.8.3 lock2: abnormal kt for any given motor, the integrated value of bemf during half of an electrical cycle is constant. the value is determined by the bemf constant (kt ph ) (see figure 36 ). the bemf constant is the same regardless of whether the motor is running fast or slow. this constant value is continuously monitored by calculation and used as a criterion to determine the motor lock condition, and is referred to as ktc. based on the kt ph value programmed, create a range from kt_low to kt_high. if ktc goes beyond the range for a certain period of time, t lck_etr , lock is detected. kt_low and kt_high are determined by ktlckthr[1:0] (see figure 37 ). bemf2 = kt speed i v u bemf1 = v C i rm u lock detected if bemf2 > v u rm m copyright ? 2017, texas instruments incorporated dac + digitalcore C
42 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 36. bemf integration figure 37. abnormal-kt lock detect 8.4.8.4 lock3: no-motor fault the phase u current is checked after transitioning from open loop to closed loop. if the phase u current is not greater than 140 ma then the motor is not connected as shown in figure 38 . this condition is treated and reported as a fault. figure 38. no-motor error 8.4.8.5 lock4: open-loop motor-stuck lock lock4 is used to detect locked-motor conditions while the motor start sequence is in open loop. for a successful startup, motor speed should be equal to the open-to-closed-loop handoff threshold when the motor is transitioning into closed loop. however, if the motor is locked, the motor speed is not able to match the open-loop drive rate. if the motor bemf is not detected for one electrical cycle after the open-loop drive rate exceeds the threshold, then the open loop was unsuccessful as a result of a locked-rotor condition. 8.4.8.6 lock5: closed-loop motor-stuck lock if the motor suddenly becomes locked, motor speed and ktc are not able to be refreshed because the bemf zero cross of the motor may not appear after the lock. in this condition, lock can also be detected by the following scheme: if the current commutation period is 2 longer than the previous period. DRV10987 m kt ktc lock detect kt_low kt_high
43 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.4.9 anti-voltage surge function when a motor is driven, energy is transferred from the power supply into the motor. some of this energy is stored in the form of inductive energy or as mechanical energy. the DRV10987 device includes circuits to prevent this energy from being returned to the power supply, which could result in pumping up the v cc voltage. this function is referred to as the avs and acts to protect the DRV10987 device as well as other circuits that share the same v cc connection. two forms of avs protection are used to prevent both the mechanical energy and the inductive energy from being returned to the supply. each of these modes can be independently disabled through the register configuration bits avsmen and avsinden. 8.4.9.1 mechanical avs function if the speed command suddenly drops such that the bemf voltage generated by the motor is greater than the voltage that is applied to the motor, then the mechanical energy of the motor is returned to the power supply and the v cc voltage surges. the mechanical avs function works to prevent this from happening. the DRV10987 device buffers the speed command value and limits the resulting output voltage, v u_min , so that it is not less than the bemf voltage of the motor. the bemf voltage in the mechanical avs function is determined using the programmed value for the motor kt (kt[6:0]) along with the speed. figure 39 shows the criteria used by the mechanical avs function. figure 39. mechanical avs the mechanical avs function can operate in one of two modes, which can be configured by the register bit avsmmd: ? avsmmd = 0 ? avs mode is always active to prevent the applied voltage from being less than the bemf voltage. ? avsmmd = 1 ? avs mode becomes active when v cc reaches 24 v. the motor acts as a generator and returns energy into the power supply until v cc reaches 24 v. this mode can be used to enable faster deceleration of the motor in applications where returning energy to the power supply is allowed. 8.4.9.2 inductive avs function when the DRV10987 device transitions from driving the motor into a high-impedance state, the inductive current in the motor windings continues to flow and the energy returns to the power supply through the intrinsic body diodes in the fet output stage (see figure 40 ). figure 40. inductive-mode voltage surge to prevent the inductive energy from being returned to the power supply, the DRV10987 system transitions from driving to a high-impedance state by first turning off the active high-side drivers, and turning on all low-side drivers. the DRV10987 device monitors phase current after entering the brake state and transitions into the high-impedance state when the amplitude of the phase current is less than brkcurthrsel for a fixed period of time (brkdonethr[2:0])(see figure 41 ). i = 0 min v u v = bemf + i rm = bemf u _min min rm m bemf copyright ? 2017, texas instruments incorporated s1s2 v cc v cc s3s4 s5s6 s1s2 s3s4 s5s6 driving state high-impedance state m m
44 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 41. inductive avs in this example, current is applied to the motor through the high-side driver on phase u (s1) and returned through the low-side driver on phase w (s6). the high-side driver on phase u is turned off' and all low-side drivers are tunned on to allow the inductive energy in the resulting lr circuit to decay. if brkdonethr[2:0] = 000, no brake is applied and the device does not protect from inductive energy even with the inductive avs feature enabled. 8.4.10 pwm output the DRV10987 device has 32 options for pwm dead time. these options can be used to configure the time between one of the bridge fets turning off and the complementary fet turning on. deadtime[4:0] can be used to configure dead times between 40 and 1280 ns. take care that the dead time is long enough to prevent the bridge fets from shooting through. the DRV10987 device offers two options for pwm switching frequency. when the configuration bit pwmfreq is set to 0, the output pwm frequency is 25 khz, and when pwmfreq is set to 1, the output pwm frequency is 50 khz. 8.4.11 fg customized configuration the DRV10987 device provides information about the motor speed through the frequency generate (fg) pin. fg also provides information about the driving state of the DRV10987 device. 8.4.11.1 fg configuration the fg output frequency can be configured by fgcycle[3:0]. the default fg toggles once every electrical cycle (fgcycle = 0000). many applications configure the fg output so that it provides two pulses for every mechanical rotation of the motor. the configuration bits provided in the DRV10987 device can accomplish this for 2-pole, 4- pole, 6-pole, and 8-pole motors up to 32-pole motors. this is illustrated in figure 42 for 2, 4, 6, and 8-pole motors. figure 42 shows the DRV10987 device has been configured to provide fg pulses once every electrical cycle (4 poles), twice every three electrical cycles (6 poles), and once every two electrical cycles (8 poles). driving s1s2 s3s4 s5s6 s1s2 s3s4 s5s6 avs state m m v cc v cc
45 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 42. fg divider 8.4.11.2 fg open-loop and lock behavior note that the fg output reflects the driving state of the motor. during normal closed-loop behavior, the driving state and the actual state of the motor are synchronized. during open-loop acceleration, however, this may not reflect the actual motor speed. during a locked-motor condition, the fg output is driven high. the DRV10987 device provides three options for controlling the fg output during open loop, as shown in figure 43 . the selection of these options is determined by the fgolsel[1:0] setting. ? option0: open-loop, fg output based on driving frequency ? option1: open-loop, no fg output (keep high) ? option2: fg output based on driving frequency at the first power-on start-up, and no fg output (keep high) for any subsequent restarts motor phase driving voltage fgcycle = 0000 2 pole fgcycle = 0001 4 pole fgcycle = 0010 6 pole fgcycle = 0011 8 pole
46 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 43. fg behavior during open loop 8.4.12 diagnostics and visibility the DRV10987 device offers extensive visibility into the motor system operation conditions stored in internal registers. this information can be monitored through the i 2 c interface. information can be monitored relating to the device status, motor speed, supply voltage, speed command, motor phase-voltage amplitude, fault status, and others. the data is updated on the fly. 8.4.12.1 motor-status readback the motor faultreg register provides information on overtemperature (overtemp), overcurrent (overcurr), and locked rotor (lock0 ? lock5). 8.4.12.2 motor-speed readback the motor operation speed is automatically updated in register motorspeed while the motor is spinning. the value is determined by the period for calculated bemf zero crossings on phase u. the electrical speed of the motor is denoted as velocity (hz) and is calculated as shown in equation 9 . velocity (hz) = {motorspeed} / 10 (9) as an example consider the following: motorspeed = 0x01ff; velocity = 512 (0x01ff) / 10 = 51 hz for a 4-pole motor, this translates to: ecycles 1 mechcycle sec ond 51 60 1530 rpm sec ond 2 ecycle minute u u motor phase driving voltage open loop closed loop fgolsel = 00 fgolsel = 01 motor phase driving voltage open loop closed loop fgolsel = 10 open loop closed loop start-up after power on or wakeup from sleep or standby mode rest of the startups
47 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.4.12.3 motor electrical-period readback the motor-operation electrical period is automatically updated in register motorperiod while the motor is spinning. the electrical period is measured as the time between calculated bemf zero crossings for phase u. the electrical period of the motor is denoted as t ele_period ( s) and is calculated as shown in equation 10 . t ele_period ( s) = {motorperiod} 10 (10) as an example consider the following: motorperiod = 0x01ff; t ele_period = 512 (0x01ff) 10 = 5120 s the motor electrical period and motor speed satisfies the condition of equation 11 . t ele_period (s) velocity (hz) = 1 (11) 8.4.12.4 bemf constant readback for any given motor, the integrated value of bemf during half of an electronic cycle is a constant, ktc (see lock2: abnormal kt ). the integration of the motor bemf is processed periodically (updated every electrical cycle) while the motor is spinning. the result is stored in register motorkt. the relationship is shown in . ktc (v/hz) = ({motorkt} / 2) / 1090 (12) 8.4.12.5 motor estimated position by ipd after inductive sense is executed, the rotor position is detected within 60 electrical degrees of resolution. the position is stored in register ipdposition. the value stored in ipdposition corresponds to one of the six motor positions plus the ipd advance angle as shown in table 8 . for more information about ipd, see initial position detect (ipd) . table 8. ipd position read back rotor position ( ) 0 60 120 180 240 300 data1 0 43 85 128 171 213 ipd advance angle 30 60 90 120 data2 22 44 63 85 register data (data1 + data2) mod (256) 8.4.12.6 supply-voltage readback the power supply is monitored periodically during motor operation. this information is available in register supplyvoltage. the power supply voltage is recorded as shown in equation 13 . v powersupply (v) = supply voltage 30 v / 256 (13) u v w n s u v w n s u v w u v w u v w u v w
48 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.4.12.7 speed-command readback the DRV10987 device converts the various types of speed command into a speed command value (speedcmd) as shown in figure 44 . by reading speedcmd, the user can observe pwm input duty cycle (pwm digital mode), analog voltage (analog mode), or i 2 c data (i 2 c mode). this value is calculated as shown in equation 14 . equation 14 shows how the speed command as a percentage can be calculated and set in speedcmd. duty speed (%) = speedcmd 100 / 255 where ? duty speed = speed command as a percentage ? speedcmd = register value (14) 8.4.12.8 speed-command buffer readback if software current limit and avs are enabled, the pwm duty cycle output (read back at spdcmdbuffer) may not always match the input command (read back at speedcmd) shown in figure 44 . see anti-voltage surge function and current limits . by reading the value of spdcmdbuffer, the user can observe buffered speed command (output pwm duty cycle) to the motor. equation 15 shows how the buffered speed is calculated. duty output (%) = spdcmdbuffer 100 / 255 where ? duty output = the maximum duty cycle of the output pwm, which represents the output amplitude as a percentage. ? spdcmdbuffer = register value (15) figure 44. speedcmd and spdcmdbuffer registers 8.4.12.9 fault diagnostics see lock detect and fault handling . pwm in speed pin analog i 2 c pwm_dco avs, software current limit closed loop accelerate pwm duty adc speed command speedcmd spdcmdbuffer copyright ? 2017, texas instruments incorporated
49 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) read only (2) fault register requires 0xff to be written to the register to clear the bits. (3) r/w 8.5 register maps 8.5.1 i 2 c serial interface the DRV10987 device provides an i 2 c slave interface with slave address 101 0010. ti recommends a pullup resistor of 4.7 k to 3.3 v for i 2 c interface ports scl and sda. the protocol for the i 2 c interface is given in figure 45 . figure 45. i 2 c protocol seven read/write registers (0x30:0x36) are used to set motor speed and control device registers and eeprom. device operation status can be read back through nine read-only registers (0x0:0x08). another seven eeprom registers (0x90:0x96) can be accessed to program motor parameters and optimize the spin-up profile for the application. 8.5.2 register map register name addr. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 faultreg (1) (2) 0x00 overtemp tempwarni ng vcc_ov vreg_oc overcurr cp_uvlo vreg_uvl o vcc_uvlo v3p3_uvl o reserved lock5 lock4 lock3 lock2 lock1 lock0 motorspeed (1) 0x01 motorspeed[15:0] motorperiod (1) 0x02 motorperiod[15:0] motorkt (1) 0x03 motorkt[15:0] motorcurrent (1) 0x04 reserved motorcurrent[10:8] motorcurrent[7:0] ipdposition / supplyvoltage (1) 0x05 ipdposition[7:0] supplyvoltage[7:0] speedcmd / spdcmdbuffer (1) 0x06 speedcmd[7:0] spdcmdbuffer[7:0] analoginlvl (1) 0x07 reserved commandsenseadc[9:8] commandsenseadc[7:0] device id / revision id (1) 0x08 dieid[7:0] revisionid[7:0] speedctrl (3) 0x30 override reserved speedctrl[8 ] speedctrl[7:0] eeprom programming1 (3) 0x31 enprogkey[15:0] start 7 bit slave add r/w=0 8 bit reg add ack ack 8 bit data ack 8 bit data ack stop internal reg write happens i2c write start 7 bit slave add r/w=0 8 bit reg add ack ack 8 bit data ack 8 bit data ack stop data from reg is loaded to the buffer i2c read start 7 bit slave add r/w=1
50 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated register maps (continued) register name addr. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (4) eeprom eeprom programming2 (3) 0x32 reserved reserved eereadyst atus eeprom programming3 (3) 0x33 reserved eeindaddress[7:0] eeprom programming4 (3) 0x34 eeindwdata[15:0] eeprom programming5 (3) 0x35 reserved shadowre gen reserved eerefresh reserved eewrnen eeaccmode[1:0] eeprom programming6 (3) 0x36 eeindrdata[15:0] eectrl 0x60 mtr_dis reserved reserved config1 (4) 0x90 ssmconfig[1:0] fgolsel[1:0] fgcycle[3:0] clkcycleadj ust rmshift[2:0] rmvalue[3:0] config2 (4) 0x91 reserved ktshift[2:0] ktvalue[3:0] commadv mode tctrladvshift[2:0] tctrladvvalue[3:0] config3 (4) 0x92 isdthr[1:0] brkcurrthr sel bemf_hys isden rvsdren rvsdrthr[1:0] openlcurr[1:0] oplcurrrt[2:0] brkdonethr[2:0] config4 (4) 0x93 reserved accelrange sel staccel2[2:0] staccel[2:0] op2clsthr[4:0] aligntime[2:0] config5 (4) 0x94 otwarning_ilimit[1:0] locken5 locken4 locken3 locken2 locken1 locken0 swilimit[3:0] hwilimit[2:0] ipdashwili mit config6 (4) 0x95 spdctlrmd pwmfreq ktlckthr[1:0] avsinden avsmen avsmmd ipdrismd cloopdis clslpaccel[2:0] dutycyclelimit[1:0] slewrate[1:0] config7 (4) 0x96 ipdadvcag[1:0] ipdcurrthr[3:0] ipdclk[1:0] reserved ctrlcoef[1:0] deadtime[4:0]
51 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated table 9. default eeprom values address default value 0x90 0xc000 0x91 0x0049 0x92 0x00c1 0x93 0x3788 0x94 0x3baf 0x95 0x7840 0x96 0x007a 8.5.3 register descriptions table 10. access type codes access type code description read type r r read write type w w write w1c w 1c write 1 to clear reset or default value - n value after reset or the default value 8.5.3.1 faultreg register (address = 0x00) [reset = 0x00] figure 46. faultreg register 15 14 13 12 11 10 9 8 overtemp tempwarning vcc_ov vreg_oc overcurr cp_uvlo vreg_uvlo vcc_uvlo r/w1c-0 r//w1c-0 r/w1c-0 r/w1c-0 r/w1c-0 r/w1c-0 r/w1c-0 r/w1c-0 7 6 5 4 3 2 1 0 v3p3_uvlo reserved lock5 lock4 lock3 lock2 lock1 lock0 r/w1c-0 r/w1c-0 r/w1c-0 r/w1c-0 r/w1c-0 r/w1c-0 r/w1c-0 r/w1c-0 table 11. faultreg register field descriptions bit field type reset description 15 overtemp r//w1c 0 bit to indicate device temperature is over the limit. 14 tempwarning r/w1c 0 bit to indicate device temperature is over the warning limit. 13 vcc_ov r/w1c 0 bit to indicate the supply voltage is above the upper limit. 12 vreg_oc r/w1c 0 bit to indicate that the switching regulator is in an overcurrent condition. 11 overcurr r/w1c 0 bit to indicate that an overcurrent event happened. 10 cp_uvlo r/w1c 0 bit to indicate that the charge pump is in an undervoltage fault condition. 9 vreg_uvlo r/w1c 0 bit to indicate that the switching regulator (vreg) is in an undervoltage fault condition. 8 vcc_uvlo r/w1c 0 bit to indicate that the supply (v cc ) is in an undervoltage fault condition. 7 v3p3_uvlo r/w1c 0 bit to indicate that the 3.3 v ldo regulator is in an undervoltage fault condition. 6 reserved r/w1c 0 do not access this bit.
52 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated table 11. faultreg register field descriptions (continued) bit field type reset description 5 lock5 r/w1c 0 stuck in closed loop fault 4 lock4 r/w1c 0 stuck in open loop fault 3 lock3 r/w1c 0 no motor fault 2 lock2 r/w1c 0 kt abnormal fault 1 lock1 r/w1c 0 speed abnormal fault 0 lock0 r/w1c 0 hardware current-limit fault 8.5.3.2 motorspeed register (address = 0x01) [reset = 0x00] figure 47. motorspeed register 15 14 13 12 11 10 9 8 motorspeed[15] motorspeed[14] motorspeed[13] motorspeed[12] motorspeed[11] motorspeed[10] motorspeed[9] motorspeed[8] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 motorspeed[7] motorspeed[6] motorspeed[5] motorspeed[4] motorspeed[3] motorspeed[2] motorspeed[1] motorspeed[0] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 table 12. motorspeed register field descriptions bit field type reset description 15:0 motorspeed[15:0] r 0x00 16-bit value indicating the motor speed. motor speed in hz = motorspeed[15:0] / 10 8.5.3.3 motorperiod register (address = 0x02) [reset = 0x00] figure 48. motorperiod register 15 14 13 12 11 10 9 8 motorperiod[15] motorperiod[14] motorperiod[13] motorperiod[12] motorperiod[11] motorperiod[10] motorperiod[9] motorperiod[8] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 motorperiod[7] motorperiod[6] motorperiod[5] motorperiod[4] motorperiod[3] motorperiod[2] motorperiod[1] motorperiod[0] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 table 13. motorperiod register field descriptions bit field type reset description 15:0 motorperiod[15:0] r 0x00 16-bit value indicating the motor period. motor period = motorperiod[15:0] 10 = period in s
53 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.3.4 motorkt register (address = 0x03) [reset = 0x00] figure 49. motorkt register 15 14 13 12 11 10 9 8 motorkt[15] motorkt[14] motorkt[13] motorkt[12] motorkt[11] motorkt[10] motorkt[9] motorkt[8] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 motorkt[7] motorkt[6] motorkt[5] motorkt[4] motorkt[3] motorkt[2] motorkt[1] motorkt[0] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 table 14. motorkt register field descriptions bit field type reset description 15:0 motorkt[15:0] r 0x00 16-bit value indicating the motor measured bemf.constant ktc (v/hz) = {motorkt[15:0]} / 2 / 1090 8.5.3.5 motorcurrent register (address = 0x04) [reset = 0x00] figure 50. motorcurrent register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved motorcurrent[1 0] motorcurrent[9] motorcurrent[8] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 motorcurrent[7] motorcurrent[6] motorcurrent[5] motorcurrent[4] motorcurrent[3] motorcurrent[2] motorcurrent[1] motorcurrent[0] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 table 15. motorcurrent register field descriptions bit field type reset description 15:11 reserved r 0 do not access these bits. 10:0 motorcurrent[10:0] r 0x00 11-bit value indicating the motor current. current (a) = 3 (motorcurrent[10:0] ? - 1023) / 2048 8.5.3.6 ipdposition ? supplyvoltage register (address = 0x05) [reset = 0x00] figure 51. ipdposition ? supplyvoltage register 15 14 13 12 11 10 9 8 ipdposition [7] ipdposition [6] ipdposition [5] ipdposition [4] ipdposition [3] ipdposition [2] ipdposition [1] ipdposition [0] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 supplyvoltage[ 7] supplyvoltage[ 6] supplyvoltage[ 5] supplyvoltage[ 4] supplyvoltage[ 3] supplyvoltage[ 2] supplyvoltage[ 1] supplyvoltage[ 0] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 table 16. ipdposition ? supplyvoltage register field descriptions bit field type reset description 15:8 ipdposition [7:0] r 0x0 8-bit value indicating the estimated motor position during ipd plus the ipd advance angle (see table 8 ) 7:0 supplyvoltage[7:0] r 0x0 8-bit value indicating the supply voltage v powersupply (v) = supplyvoltage[7:0] 30 v / 255 for example, supplyvoltage[7:0] = 0x67, v powersupply (v) = 0x67 (102) 30 / 255 = 12 v
54 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.3.7 speedcmd ? spdcmdbuffer register (address = 0x06) [reset = 0x00] figure 52. speedcmd ? spdcmdbuffer register 15 14 13 12 11 10 9 8 speedcmd[7] speedcmd[6] speedcmd[5] speedcmd[4] speedcmd[3] speedcmd[2] speedcmd[1] speedcmd[0] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 spdcmdbuffer[[ 7] spdcmdbuffer[[ 6] spdcmdbuffer[[ 5] spdcmdbuffer[[ 4] spdcmdbuffer[[ 3] spdcmdbuffer[[ 2] spdcmdbuffer[[ 1] spdcmdbuffer[[ 0] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 table 17. speedcmd ? spdcmdbuffer register field descriptions bit field type reset description 15:8 speedcmd[7:0] r 0x0 8-bit value indicating the speed command based on analog or pwmin or i 2 c. ff indicates 100% speed command. 7:0 spdcmdbuffer[7:0] r 0x0 8-bit value indicating the speed command after buffer output. ff indicates 100% speed command. 8.5.3.8 analoginlvl register (address = 0x07) [reset = 0x00] figure 53. analoginlvl register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved commandsnsa dc[9] commandsnsa dct[8] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 commandsnsa dc[7] commandsnsa dc[6] commandsnsa dc[5] commandsnsa dc[4] commandsnsa dc[3] commandsnsa dc[2] commandsnsa dc[1] commandsnsa dc[0] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 table 18. analoginlvl register field descriptions bit field type reset description 15:10 reserved r 0 do not access these bits. 9:0 commandsnsadc[9:0] r 0x00 10-bit value indicating the analog speed input converted to a digital word. analogspeed (v) = analoginlvl v3p3 / 1024 8.5.3.9 deviceid ? revisionid register (address = 0x08) [reset = 0x00] figure 54. deviceid ? revisionid register 15 14 13 12 11 10 9 8 dieid[7] dieid[6] dieid[5] dieid[4] dieid[3] dieid[2] dieid[1] dieid[0] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 revisionid[7] revisionid[6] revisionid[5] revisionid[4] revisionid[3] revisionid[2] revisionid[1] revisionid[0] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
55 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated table 19. deviceid ? revisionid register field descriptions bit field type reset description 15:8 dieid[7:0] r 0x0 8-bit unique device identification. 7:0 revisionid[7:0] r 0x0 8-bit revision id for the device 0000 0000 rev a 0000 0001 rev b ... 8.5.3.10 unused registers (addresses = 0x011 through 0x2f) registers 0x09 through 0x2f are not used. 8.5.3.11 speedctrl register (address = 0x30) [reset = 0x00] figure 55. speedctrl register 15 14 13 12 11 10 9 8 override reserved reserved reserved reserved reserved reserved speedctrl[8] r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 r/w-0 7 6 5 4 3 2 1 0 speedctrl[7] speedctrl[6] speedctrl[5] speedctrl[4] speedctr[3] speedctrl[2] speedctrl[1] speedctrl[0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 table 20. speedctrl register field descriptions bit field type reset description 15 override r/w 0 used to control the spdctrl[8:0] bits. if override = 1, the user can write the speed command directly through i 2 c. 14:9 reserved r 0x0 do not access these bits. 8:0 speedctrl[8:0] r/w 0x00 9-bit value used for the motor speed. if override = 1, speed command can be written by the user through i 2 c.
56 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.3.12 eeprom programming1 register (address = 0x31) [reset = 0x00] figure 56. eeprom programming1 register 15 14 13 12 11 10 9 8 enprogkey [15] enprogkey [14] enprogkey [13] enprogkey [12] enprogkey [11] enprogkey [10] enprogkey [9] enprogkey [9] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 6 5 4 3 2 1 0 enprogkey [7] enprogkey [6] enprogkey [5] enprogkey [4] enprogkey [3] enprogkey [2] enprogkey [1] enprogkey [0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 table 21. eeprom programming1 register field descriptions bit field type reset description 15:0 enprogkey[15:0] r/w 0x00 eeprom access key 0xcode access key for customer space; registers 0x90 to 0x96 8.5.3.13 eeprom programming2 register (address = 0x32) [reset = 0x00] figure 57. eeprom programming2 register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved reserved reserved eereadystatus r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 table 22. eeprom programming2 register field descriptions bit field type reset description 15:1 reserved r 0x00 do not access these bits. 0 eereadystatus r 0 eeprom status bit. 0: eeprom not ready for read/write access 1: eeprom ready for read/write access 8.5.3.14 eeprom programming3 register (address = 0x33) [reset = 0x00] figure 58. eeprom programming3 register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved reserved r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 eeindaddress [7] eeindaddress [6] eeindaddress [5] eeindaddress [4] eeindaddress [3] eeindaddress [2] eeindaddress [1] eeindaddress [0] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
57 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated table 23. eeprom programming3 register field descriptions bit field type reset description 15:8 reserved r 0x0 do not access these bits. 7:0 eeindaddress[7:0] r 0x0 eeprom individual access address. contents of this register define the address of eeprom for the individual access operation. for example, for writing/reading config1 in individual access mode happens if eeindaddress = 0x90. 8.5.3.15 eeprom programming4 register (address = 0x34) [reset = 0x00] figure 59. eeprom programming4 register 15 14 13 12 11 10 9 8 eeindwdata [15] eeindwdata [14] eeindwdata [13] eeindwdata [12] eeindwdata [11] eeindwdata [10] eeindwdata[9] eeindwdata[8] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 6 5 4 3 2 1 0 eeindwdata[7] eeindwdata[6] eeindwdata[5] eeindwdata[4] eeindwdata[3] eeindwdata[2] eeindwdata[1] eeindwdata[0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 table 24. eeprom programming4 register field descriptions bit field type reset description 15:0 eeindwdata[15:0] r/w 0x00 eeprom individual access write data contents of this register are the data to be written to eeprom of the registers specified by eeindaddress. 8.5.3.16 eeprom programming5 register (address = 0xyy) [reset = 0x00] figure 60. eeprom programming5 register 15 14 13 12 11 10 9 8 reserved reserved reserved shadowregen reserved reserved reserved eerefresh r-0 r-0 r-0 r/w-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved eewrnen eeaccmode[1] eeaccmode[0] r-0 r-0 r-0 r-0 r-0 r/w-0 r/w-0 r/w-0 table 25. eeprom programming5 register field descriptions bit field type reset description 15:13 reserved r 000 do not access these bits. 12 shadowregen r/w 0 enable shadow register. 0: shadow register is not used. 1: shadow register values are used for device operation (eeprom contents are ignored). i 2 c read returns the contents of the shadow registers. 11:9 reserved r 000 do not access these bits. 8 eerefresh r/w 0 eeprom refresh 0: normal operation 1: sync shadow registers with contents of eeprom. 7:3 reserved r 0x0 do not access these bits. 2 eewrnen r/w 0 eeprom refresh 0: normal operation 1: sync shadow registers with contents of eeprom.
58 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated table 25. eeprom programming5 register field descriptions (continued) bit field type reset description 1:0 eeaccmode[1:0] r/w 00 eeprom access mode 00: eeprom access disabled 01: eeprom individual access enabled 10: eeprom mass access enabled 11: reserved 8.5.3.17 eeprom programming6 register (address = 0x36) [reset = 0x00] figure 61. eeprom programming6 register 15 14 13 12 11 10 9 8 eeindrdata[15] eeindrdata[14] eeindrdata[13] eeindrdata[12] eeindrdata[11] eeindrdata[10] eeindrdata[9] eeindrdata[8] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 eeindrdata[7] eeindrdata[6] eeindrdata[5] eeindrdata[4] eeindrdata[3] eeindrdata[2] eeindrdata[1] eeindrdata[0] r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 table 26. eeprom programming6 register field descriptions bit field type reset description 15:0 eeindrdata[15:0] r 0x00 eeprom individual access read data contents of this register reflect the value of eeprom location accessed through the individual read. 8.5.3.18 unused registers (addresses = 0x37 through 0x5f) registers 0x37 through 0x5f are not used. 8.5.3.19 eectrl register (address = 0x60) [reset = 0x00] figure 62. eectrl register 15 14 13 12 11 10 9 8 mtr_dis reserved reserved reserved reserved reserved reserved reserved w-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved reserved reserved reserved r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 table 27. eectrl register field descriptions bit field type reset description 15 mtr_dis w 0 control to disable motor operation. for use during eeprom programming. this bit is write-only (cannot be read). 0: motor control is enabled. 1: motor control is disabled. 14:0 reserved r 0x00 reserved 8.5.3.20 unused registers (addresses = 0x61 through 0x8f) registers 0x61 through 0x8f are not used.
59 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.3.21 config1 register (address = 0x90) [reset = 0x00] figure 63. config1 register 15 14 13 12 11 10 9 8 ssmconfig[1] ssmconfig[0] fgolsel[1] fgolsel[0] fgcycle[3] fgcycle[2] fgcycle[1] fgcycle[0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 6 5 4 3 2 1 0 clkcycleadjust rmshift[2] rmshift[1] rmshift[0] rmvalue[3] rmvalue[2] rmvalue[1] rmvalue[0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 table 28. config1 register field descriptions bit field type reset description 15:14 ssmconfig[1:0] r/w 00 spread spectrum modulation control 00: no spread spectrum 01: 5% dithering 1:0: 10% dithering 11: 15% dithering 13:12 fgolsel[1:0] r/w 00 fg open-loop output select 00: fg outputs in both open loop and closed loop 01: fg outputs only in closed loop 10: fg outputs closed loop and the first open loop 11: reserved 11:8 fgcycle[3:0] r/w 0x0 fg motor pole option n: fg output is electrical speed / (n + 1) 0: fg / 1 (2 pole) 1: fg / 2 (4 pole) 2: fg / 3 (6 pole) 3: fg / 4 (8 pole) ... 15: fg / 16 (32 pole) 7 clkcycleadjust r/w 0 0: full-cycle adjust 1: half-cycle adjust 6:4 rmshift[2:0] r/w 000 number of shift bits to determine the motor phase resistance. rm = rmvalue < < rmshift rm' = (bin) {rphase / 0.009615} after calculating rm' value, split the value with shift number and significant number according the length of the rm' value. if the length of rm' is within 4 bits; rmvalue[3:0] = rm'; rmshift[2:0] = 000 if the length of rm' is 5 bits; rmvalue[3:0] = rm'[4:1]; rmshift[2:0] = 001 and so on. 3:0 rmvalue[3:0] r/w 0x0 significant portion of the motor resistor, used in conjunction with rmshift[2:0] 8.5.3.22 config2 register (address = 0x91) [reset = 0x00] figure 64. config2 register 15 14 13 12 11 10 9 8 reserved ktshift[2] ktshift[1] ktshift[0] ktvalue[3] ktvalue[2] ktvalue[1] ktvalue[0] r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 6 5 4 3 2 1 0 commadvmod e tctrladvshift[2] tctrladvshift[1] tctrladvshift[0] tctrladvvalue[3:0] r/w-0 r/w-0 r/w-0 r/w-0 r-0
60 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) eeprom table 29. config2 register field descriptions bit field type reset description 15 reserved r 0 do not access this bit 14:12 ktshift[2:0] r/w 000 number of shift bits to determine the motor bemf constant. kt = ktvalue < < ktshift 11:8 ktvalue[3:0] r/w 0x0 7 commadvmode r/w 0 commutation advance mode 0: voltage advance is maintained at a fixed time (1) relative to the estimated bemf. 1: voltage advance is maintained at a variable time relative to the estimated bemf based on: t adv = t setting (v u(bemf) ) / v u 6:4 tctrladvshift[2:0] r/w 000 number of shift bits to determine the commutation advance timing t adv = tctrladvvalue < < tctrladvshift 3:0 tctrladvvalue[3:0] r/w 0x0 commutation advance value. 8.5.3.23 config3 register (address = 0x92) [reset = 0x00] figure 65. config3 register 15 14 13 12 11 10 9 8 isdthr[1] isdthr[0] brkcurthrsel bemf_hys isden rvsdren rvsdrthr[1] rvsdrthr[0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 6 5 4 3 2 1 0 openlcurr[1] openlcurr[0] oplcurrrt[2] oplcurrrt[1] oplcurrrt[0] brkdonethr[2] brkdonethr[1] brkdonethr[0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 table 30. config3 register field descriptions bit field type reset description 15:14 isdthr[1:0] r/w 00 isd stationary judgment threshold 00: 6 hz (80 ms, no zero cross) 01: 3 hz (160 ms, no zero cross) 10: 1.6 hz (320 ms, no zero cross) 11: 0.8 hz (640 ms, no zero cross) 13 brkcurthrsel r/w 0 brake current-level-threshold selection. 0: 24 ma 1: 48 ma 12 bemf_hys r/w 0 0: low hysteresis for bemf comparator (approximately 10 mv) 1: high hysteresis for bemf comparator (approximately 20 mv) 11 isden r/w 0 0: initial speed detect (isd) disabled 1: isd enabled 10 rvsdren r/w 0 0: reverse drive disabled 1: reverse drive enabled 9:8 rvsdrthr[1:0] r/w 00 the threshold where device starts to process reverse drive (rvsdr) or brake. 00: 6.3 hz 01: 13 hz 10: 26 hz 11: 51 hz
61 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated table 30. config3 register field descriptions (continued) bit field type reset description 7:6 openlcurr[1:0] r/w 00 open-loop current setting. 00: 0.2 a 01: 0.4 a 10: 0.8 a 11: 1.6 a align current setting. 00: 0.15 a 01: 0.3 a 10: 0.6 a 11: 1.2 a 5:3 oplcurrrt[2:0] r/w 000 open-loop current ramp-up setting. 000: 6 v cc /s 001: 3 v cc /s 010: 1.5 v cc /s 011: 0.7 v cc /s 100: 0.34 v cc /s 101: 0.16 v cc /s 110: 0.07 v cc /s 111: 0.023 v cc /s 2:0 brkdonethr[2:0] r/w 000 braking mode setting. 000: no brake (brken = 0) 001: 2.7 s 010: 1.3 s 011: 0.67 s 100: 0.33 s 101: 0.16 s 110: 0.08 s 111: 0.04 s 8.5.3.24 config4 register (address = 0x93) [reset = 0x00] figure 66. config4 register 15 14 13 12 11 10 9 8 reserved accelrangesel staccel2[2] staccel2[1] staccel2[0] staccel[2] staccel[1] staccel[0] r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 6 5 4 3 2 1 0 op2clsthr[4] op2clsthr[3] op2clsthr[2] op2clsthr[1] op2clsthr[0] aligntime[2] aligntime[1] aligntime[0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0
62 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated table 31. config4 register field descriptions bit field type reset description 15 reserved r 0 do not access this bit 14 accelrangesel r/w 0 acceleration range selection 0: fast 1: slow 13:11 staccel2[2:0] r/w 000 open-loop start-up acceleration (second-order acceleration coefficient) accelrangesel = 0; 000: 57 hz/s 2 accelrangesel = 0; 001 = 29 hz/s 2 accelrangesel = 0; 010 = 14 hz/s 2 accelrangesel = 0; 011 = 6.9 hz/s 2 accelrangesel = 0; 100 = 3.3 hz/s 2 accelrangesel = 0; 101 = 1.6 hz/s 2 accelrangesel = 0; 110 = 0.66 hz/s 2 accelrangesel = 0; 111 = 0 hz/s 2 accelrangesel = 1; 000 = 0.22 hz/s 2 accelrangesel = 1; 001 = 0.11 hz/s 2 accelrangesel = 1; 010 = 0.055 hz/s 2 accelrangesel = 1; 011 = 0.027 hz/s 2 accelrangesel = 1; 100 = 0.013 hz/s 2 accelrangesel = 1; 101 = 0.0063 hz/s 2 accelrangesel = 1; 110 = 0.0026 hz/s 2 accelrangesel = 1; 111 = 0 hz/s 2 10:8 staccel[2:0] r/w 0 open-loop start-up acceleration (first-order acceleration coefficient) accelrangesel = 0; 000 = 76 hz/s accelrangesel = 0; 001 = 38 hz/s accelrangesel = 0; 010 = 19 hz/s accelrangesel = 0; 011 = 9.2 hz/s accelrangesel = 0; 100 = 4.5 hz/s accelrangesel = 0; 101 = 2.1 hz/s accelrangesel = 0; 110 = 0.9 hz/s accelrangesel = 0; 111 = 0.3 hz/s accelrangesel = 1; 000 = 4.8 hz/s accelrangesel = 1; 001 = 2.4 hz/s accelrangesel = 1; 010 = 1.2 hz/s accelrangesel = 1; 011 = 0.58 hz/s accelrangesel = 1; 100 = 0.28 hz/s accelrangesel = 1; 101 = 0.13 hz/s accelrangesel = 1; 110 = 0.056 hz/s accelrangesel = 1; 111 = 0.019 hz/s 7:3 op2clsthr[4:0] r/w 0 open- to closed-loop threshold 0 xxxx = range 0: n 0.8 hz 0 0000 = n/a 0 0001 = 0.8 hz 0 0111 = 5.6 hz 0 1111 = 12 hz 1 xxxx = range 1: (n + 1) 12.8 hz 1 0000 = 12.8 hz 1 0001 = 25.6 hz ... 1 0111 = 192 hz 1 1111 = 204.8 hz 2:0 aligntime[2:0] r/w 0 align time. 000 = 5.3 s 001 = 2.7 s 010 = 1.3 s 011 = 0.67 s 100 = 0.33 s 101 = 0.16 s 110 = 0.08 s 111 = 0.04 s
63 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.3.25 config5 register (address = 0x94) [reset = 0x00] figure 67. config5 register 15 14 13 12 11 10 9 8 otwarning limit[1] otwarning limit[0] locken5 locken4 locken3 locken2 locken1 locken0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 6 5 4 3 2 1 0 swilimitthr [3] swilimitthr [2] swilimitthr [1] swilimitthr [0] hwilimitthr [2] hwilimitthr [1] hwilimitthr [0] ipdashwilimit r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 table 32. config5 register field descriptions bit field type reset description 15:14 otwarninglimit[1:0] r/w 00 overtemperature warning current limit 00: no temperature-based current-limit function, uses swilimitthr 01: limit current to 1 a when overtemperature warning reached 10: limit current to 1.6 a when overtemperature warning reached 11: limit current to 2 a when overtemperature warning reached 13 locken5 r/w 0 stuck in closed loop (no zero cross detected). enabled when high 12 locken4 r/w 0 open loop stuck (no zero cross detected). enabled when high 11 locken3 r/w 0 no motor fault. enabled when high 10 locken2 r/w 0 abnormal kt. enabled when high 9 locken1 r/w 0 abnormal speed. enabled when high 8 locken0 r/w 0 lock-detection current limit. enabled when high. 7:4 swilimitthr[3:0] r/w 0x0 software current limit threshold 0000: no software current limit 0001: 0.2-a current limit 0010 to 1111: n 0.2 a current limit 3:1 hwilimitthr[2:0] r/w 000 hwilimitthr: current limit for lock detection if ipdashwilimit = 0 then x00: 2.5 a x01: 1.9 a x10: 1.5 a x11: 0.9 a if ipdashwilimit = 1 then 000: 0.4 a 001: 0.8 a 010: 1.2 a 011: 1.6 a 100: 2 a 101: 2.4 a 110: 2.8 a 111: 3.2 a 0 ipdashwilimit r/w 0 0: range1 of current limit for lock detection 1: range2 of current limit for lock detection
64 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.3.26 config6 register (address = 0x95) [reset = 0x00] figure 68. config6 register 15 14 13 12 11 10 9 8 spdctrlmd pwmfreq ktlckthr[1] ktlckthr[0] avsinden avsmen avsmmd ipdrlsmd r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 6 5 4 3 2 1 0 cloopdis clslpaccel[2] clslpaccel[1] clslpaccel[0] dutycyclelimit[ 1] dutycyclelimit[ 0] slewrate[1] slewrate[0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 table 33. config6 register field descriptions bit field type reset description 15 spdctrlmd r/w 0 speed input mode 0: analog input expected at speed pin 1: pwm input expected at speed pin 14 pwmfreq r/w 0 pwm frequency control 0: pwm frequency = 25 khz 1: pwm frequency = 50 khz 13:12 ktlckthr[1:0] r/w 0 abnormal kt lock detect threshold 00: kt_high = 3/2kt. kt_low = 3/4kt 01: kt_high = 2kt. kt_low = 3/4kt 10: kt_high = 3/2kt. kt_low = 1/2kt 11: kt_high = 2kt. kt_low = 1/2kt 11 avsinden r/w 0 inductive avs enable. enabled when high 10 avsmen r/w 0 mechanical avs enable. enabled when high 9 avsmmd r/w 0 mechanical avs mode 0: avs to v cc 1: avs to 24 v 8 ipdrlsmd r/w 0 ipd release mode 0: brake when inductive release 1: hi-z when inductive release 7 cloopdis r/w 0 0: transfer to closed loop at op2clsthr speed 1: no transfer to closed loop. keep in open loop 6:4 clslpaccel[2:0] r/w 0 closed-loop accelerate 000: immediate change 001: 48 v cc /s 010: 48 v cc /s 011: 0.77 v cc /s 100: 0.37 v cc /s 101: 0.19 v cc /s 110: 0.091 v cc /s 111: 0.045 v cc /s 3:2 dutycyclelimit[1:0] r/w 0 minimum duty-cycle limit 00: linear down to 5%, then holds at 5% until duty command is 1.5%; 0% for duty command below 1.5%. 01: linear down to 10%, then holds at 10% until duty command is 1.5%; 0% for duty command below 1.5%. 10: linear down to 5%, then holds at 5% until duty command is 1.5%; 100% for duty command below 1.5%. 11: linear down to 10%, then holds at 10% until duty command is 1.5%; 100% for duty command below 1.5%. 1:0 slewrate[1:0] r/w 0 slew-rate control for phase node 00: typical slew rate for v cc at 12 v = 35 v/ s 01: typical slew rate for v cc at 12 v = 50 v/ s 10: typical slew rate for v cc at 12 v = 80 v/ s 11: typical slew rate for v cc at 12 v = 120 v/ s
65 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.3.27 config7 register (address = 0x96) [reset = 0x00] figure 69. config7 register 15 14 13 12 11 10 9 8 ipdadvcag[1] ipdadvcag[0] ipdcurrthr[3] ipdcurrthr[2] ipdcurrthr[1] ipdcurrthr[0] ipdclk[1] ipdclk[0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 6 5 4 3 2 1 0 reserved ctrlcoef[1] ctrlcoef[0] deadtime[4] deadtime[3] deadtime[2] deadtime[1] deadtime[0] r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 table 34. config7 register field descriptions bit field type reset description 15:14 ipdadvcag[1:0] r/w 00 advance angle after inductive sense. 00: 30 degrees 01: 60 degrees 10: 90 degrees 11: 120 degrees 13:10 ipdcurrthr[3:0] r/w 0x0 ipd (inductive sense) current threshold 0000: no ipd function. align and go 0001: 0.4-a current threshold. 0010 to 1111: 0.2 a (n + 1) current threshold. 9:8 ipdclk[1:0] r/w 00 inductive sense clock 00: ipd clock 12 hz; ipd measurement resolution = 2.56 s 01: ipd clock = 24 hz; ipd measurement resolution = 1.28 s 10: ipd clock = 47 hz; ipd measurement resolution = 0.64 s 11: ipd clock = 95 hz; ipd measurement resolution = 0.32 s 7 reserved r 0 do not access this bit. 6:5 ctrlcoef[1:0] r/w 00 score control constant 00: 0.25 01: 0.5 10: 0.75 11: 1 4:0 deadtime[4:0] r/w 0x0 driver dead time (n + 1) 40 ns 40 ns to 1.28 s
66 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the DRV10987 device is used in sensorless 3-phase bldc motor control. the driver provides a high- performance, high-reliability, flexible, and simple solution for appliance, fan, pump, and hvac applications. the following design shows a common application of the DRV10987 device. 9.2 typical application figure 70. typical application schematic 9.2.1 design requirements table 35 provides design input parameters and motor parameters for system design. 1 2 3 4 5 6 7 89 10 11 12 24 23 22 21 20 1918 17 16 15 14 13 vcp cpp cpn sw swgnd vreg v1p8 gnd v3p3 scl sda fg vcc vcc ww vv uu pgnd pgnd dir speed interface to microcontroller 0.1 f 10 nf 47 h 10 f 1 f 10 f 1 f vcc 5 v m copyright ? 2017, texas instruments incorporated 4.75 k w 4.75 k w
67 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated typical application (continued) table 35. recommended application range min typ max unit motor voltage 6.2 12 28 v bemf constant phase to phase, measured while motor is coasting 0.001 1.8 v/hz motor phase resistance 1 phase, measured ph-ph and divided by 2 0.3 19 motor electrical constant 1 phase; inductance divided by resistance, measured ph-ph is equal to 1 ph 100 5000 s operating closed loop speed electrical frequency 1 1000 hz motor winding current (rms) 0.1 2 a absolute maximum current during start-up or locked condition 3 a table 36. external components component pin 1 pin 2 recommended c vcc v cc gnd 10- f ceramic capacitor rated for v cc c vcp vcp v cc 0.1- f ceramic capacitor rated for 10 v c cp cpp cpn 10-nf ceramic capacitor rated for v cc 2 l sw-vreg sw vreg 47- h ferrite rated for 1.15a (buck mode) r sw-vreg sw vreg 39- series resistor rated for ? w (linear mode) c vreg vreg gnd 10- f ceramic capacitor rated for 10 v c v1p8 v1p8 gnd 1- f ceramic capacitor rated for 5 v c v3p3 v3p3 gnd 1- f ceramic capacitor rated for 5 v r scl scl v3p3 4.75-k pullup to v3p3 r sda sda v3p3 4.75-k pullup to v3p3 r fg fg v3p3 4.75-k pullup to v3p3 9.2.2 detailed design procedure 1. see the design requirements section and make sure your system meets the recommended application range. 2. see the drv10983-q1 tuning guide and measure the motor parameters. 3. see the drv10983-q1 tuning guide . configure the parameters using the DRV10987 gui, and optimize the motor operation. the tuning guide takes the user through all the configurations step by step, including: start- up operation, closed-loop operation, current control, initial positioning, lock detection, and anti-voltage surge. 4. build the hardware based on layout guidelines . 5. connect the device into a system and validate your system solution.
68 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.2.3 application curves figure 71. DRV10987 start-up waveform figure 72. DRV10987 operation current waveform fg phase current phase voltage
69 DRV10987 www.ti.com slvse89a ? august 2017 ? revised november 2017 product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 10 power supply recommendations the DRV10987 device is designed to operate from an input voltage supply, v cc , in a range between 8 v and 28 v. the user must place a 10- f ceramic capacitor rated for v cc as close as possible to the v cc and gnd pins. if the power supply ripple is more than 200 mv, in addition to the local decoupling capacitors, a bulk capacitance is required and must be sized according to the application requirements. if the bulk capacitance is implemented in the application, the user can reduce the value of the local ceramic capacitor to 1 f. 11 layout 11.1 layout guidelines ? place the v cc , gnd, u, v, and w pins with thick traces because high current passes through these traces. ? place the 10- f capacitor between v cc and gnd, and as close to the v cc and gnd pins as possible. ? place the capacitor between cpp and cpn, and as close to the cpp and cpn pins as possible. ? place the capacitor between v1p8 and gnd, and as close to the v1p8 pin as possible. ? connect gnd, pgnd, and swgnd under the thermal pad. ? keep the thermal pad connection as large as possible, on both the bottom side and top sides. it should be one piece of copper without any gaps. 11.2 layout example figure 73. layout diagram fg dir speed u u v v w w v cc v cc swgnd gnd vcp cpp cpn vreg sw v1p8 v3p3 scl sda r (4.75 k ) fg w r (4.75 k ) sda w r (4.75 k ) scl w c (1 f) v3p3 c (1 f) v1p8 c (10 f) vre g c (0.1 f) vcp c (10 f) vcc c (10 nf) cp l (47 h) sw_vreg pgnd pgnd
70 DRV10987 slvse89a ? august 2017 ? revised november 2017 www.ti.com product folder links: DRV10987 submit documentation feedback copyright ? 2017, texas instruments incorporated 12 device and documentation support 12.1 trademarks powerpad, e2e are trademarks of texas instruments. is a trademark of ~other. 12.2 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most- current data available for the designated devices. this data is subject to change without notice and without revision of this document. for browser-based versions of this data sheet, see the left-hand navigation pane.
package option addendum www.ti.com 17-nov-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples DRV10987dpwpr preview htssop pwp 24 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 10987d DRV10987spwpr preview htssop pwp 24 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 10987s (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 17-nov-2017 addendum-page 2

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as is ? and with all faults. ti disclaims all other warranties or representations, express or implied, regarding resources or use thereof, including but not limited to accuracy or completeness, title, any epidemic failure warranty and any implied warranties of merchantability, fitness for a particular purpose, and non-infringement of any third party intellectual property rights. ti shall not be liable for and shall not defend or indemnify designer against any claim, including but not limited to any infringement claim that relates to or is based on any combination of products even if described in ti resources or otherwise. in no event shall ti be liable for any actual, direct, special, collateral, indirect, punitive, incidental, consequential or exemplary damages in connection with or arising out of ti resources or use thereof, and regardless of whether ti has been advised of the possibility of such damages. unless ti has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., iso/ts 16949 and iso 26262), ti is not responsible for any failure to meet such industry standard requirements. where ti specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. using products in an application does not by itself establish any safety features in the application. designers must ensure compliance with safety-related requirements and standards applicable to their applications. designer may not use any ti products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). such equipment includes, without limitation, all medical devices identified by the u.s. food and drug administration as class iii devices and equivalent classifications outside the u.s. ti may expressly designate certain products as completing a particular qualification (e.g., q100, military grade, or enhanced product). designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at designers ? own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2017, texas instruments incorporated

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